參數(shù)資料
型號： LTC2415CGN
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 24-Bit No Latency ADCs with Differential Input and Differential Reference
中文描述： 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝： 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù)： 23/40頁
文件大小： 605K
代理商： LTC2415CGN
LTC2415/LTC2415-1
23
sn2415 24151fs
APPLICATIU
W
U
U
Figure 13. Internal Serial Clock, Continuous Operation
SDO
SCK
(INTERNAL)
CS
LSB
24
MSB
SIG
BIT 5
BIT 0
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
CONVERSION
2415 F13
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
GND
SDO
CS
2
14
3
4
13
5
6
12
1, 7, 8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
2-WIRE
INTERFACE
1
μ
F
2.7V TO 5.5V
LTC2415/
LTC2415-1
= 50Hz REJECTION (LTC2415)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2415)
= 50Hz/60Hz REJECTION (LTC2415-1)
V
CC
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0), SCK
will go LOW. Once CS goes HIGH (within the time period
defined above as t
EOCtest
), the internal pull-up is activated.
For a heavy capacitive load on the SCK pin, the internal
pull-up may not be adequate to return SCK to a HIGH level
before CS goes low again. This is not a concern under
normal conditions where CS remains LOW after detecting
EOC = 0. This situation is easily overcome by adding an
external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 13. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 0.5ms after V
CC
exceeds 2.2V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
相關(guān)PDF資料
PDF描述
LTC2415IGN 24-Bit No Latency ADCs with Differential Input and Differential Reference
LTC2415 2-Channel Differential Input 24-Bit No Latency DS ADC
LTC2424 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 48-SSOP -40 to 85
LTC2424C 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 54-BGA MICROSTAR JUNIOR -40 to 85
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