參數(shù)資料
型號: LTC2415CGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 24-Bit No Latency ADCs with Differential Input and Differential Reference
中文描述: 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 36/40頁
文件大?。?/td> 605K
代理商: LTC2415CGN
LTC2415/LTC2415-1
36
sn2415 24151fs
TYPICAL APPLICATIO S
************************************************************
* This example program transfers the LTC2415/LTC2415-1 32-bit output *
* conversion result into four consecutive 8-bit memory locations. *
************************************************************
*68HC11 register definition
PORTD
EQU
$1008
Port D data register
*
" – , – , SS* ,CSK ;MOSI,MISO,TxD ,RxD"
DDRD
EQU
$1009
Port D data direction register
SPSR
EQU
$1028
SPI control register
*
"SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0"
SPSR
EQU
$1029
SPI status register
*
"SPIF,WCOL, – ,MODF; – , – , – , – "
SPDR
EQU
$102A
SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC2415/LTC2415-1’s 32 conversion result
*
DIN1
EQU
$00
This memory location holds the LTC2415/LTC2415-1’s bits 31 - 24
DIN2
EQU
$01
This memory location holds the LTC2415/LTC2415-1’s bits 23 - 16
DIN3
EQU
$02
This memory location holds the LTC2415/LTC2415-1’s bits 15 - 08
DIN4
EQU
$03
This memory location holds the LTC2415/LTC2415-1’s bits 07 - 00
*
**********************
* Start GETDATA Routine *
**********************
*
ORG
$C000
Program start location
INIT1
LDS
#$CFFF
Top of C page RAM, beginning location of stack
LDAA
#$2F
–,–,1,0;1,1,1,1
*
–, –, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X
STAA
PORTD
Keeps SS* a logic high when DDRD, bit 5 is set
LDAA
#$38
–,–,1,1;1,0,0,0
STAA
DDRD
SS*, SCK, MOSI are configured as Outputs
*
MISO, TxD, RxD are configured as Inputs
*DDRD’s bit 5 is a 1 so that port D’s SS* pin is a general output
LDAA
#$50
STAA
SPCR
The SPI is configured as Master, CPHA = 0, CPOL = 0
*
and the clock rate is E/2
*
(This assumes an E-Clock frequency of 4MHz. For higher E-
*
Clock frequencies, change the above value of $50 to a value
*
that ensures the SCK frequency is 2MHz or less.)
GETDATA PSHX
PSHY
PSHA
LDX
#$0
The X register is used as a pointer to the memory locations
*
that hold the conversion data
LDY
#$1000
BCLR
PORTD, Y %00100000
*
*
This sets the SS* output bit to a logic
low, selecting the LTC2415/LTC2415-1
相關(guān)PDF資料
PDF描述
LTC2415IGN 24-Bit No Latency ADCs with Differential Input and Differential Reference
LTC2415 2-Channel Differential Input 24-Bit No Latency DS ADC
LTC2424 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 48-SSOP -40 to 85
LTC2424C 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 54-BGA MICROSTAR JUNIOR -40 to 85
LTC2424CG 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 56-BGA MICROSTAR JUNIOR -40 to 85
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