For relatively small values of input capacitance (C
參數(shù)資料
型號(hào)： LTC2415IGN#TR
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 0K
描述： IC A/D CONV 24BIT MICRPWR 16SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 15
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
其它名稱(chēng)： LTC2415IGNTR
LTC2415/LTC2415-1
28
sn2415 24151fs
APPLICATIO S I FOR ATIO
WU
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For relatively small values of input capacitance (CIN <
0.01
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of CIN are unavoidably present as parasitics
of input multiplexers, wires, connectors or sensors, the
LTC2415/LTC2415-1 can maintain their exceptional accu-
racy while operating with relative large values of source
resistance as shown in Figures 20 and 21. These mea-
sured results may be slightly different from the first order
approximation suggested earlier because they include the
effect of the actual second order input network together
with the nonlinear settling process of the input amplifiers.
For small CIN values, the settling on IN+ and IN– occurs
almost independently and there is little benefit in trying to
match the source impedance for the two pins.
Larger values of input capacitors (CIN > 0.01F) may be
required in certain configurations for antialiasing or gen-
eral input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance.
When FO = LOW (internal oscillator and 60Hz notch), the
typical differential input resistance is 1.8M
(LTC2415),
1.97M
(LTC2415-1) which will generate a gain error of
approximately 0.28ppm for each ohm of source resis-
tance driving IN+ or IN–. For the LTC2415, when FO = HIGH
(internal oscillator and 50Hz notch), the typical differential
input resistance is 2.16M
which will generate a gain
error of approximately 0.23ppm for each ohm of source
resistance driving IN+ or IN–. When FO is driven by an
external oscillator with a frequency fEOSC (external conver-
sion clock operation), the typical differential input resis-
tance is 0.28 1012/fEOSC and each ohm of
source resistance driving IN+ or IN– will result in
1.78 10–6 fEOSCppm gain error. The effect of the source
resistance on the two input pins is additive with respect to
this gain error. The typical +FS and –FS errors as a function
of the sum of the source resistance seen by IN+ and IN– for
large values of CIN are shown in Figures 22 and 23.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional to the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modu-
lation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source imped-
ance seen by the IN+ and IN– pins. When FO = LOW
(internal oscillator and 60Hz notch), every 1
mismatch
in source impedance transforms a full-scale common
mode input signal into a differential mode input signal of
0.28ppm. When FO = HIGH (internal oscillator and 50Hz
notch), every 1
mismatch in source impedance trans-
forms a full-scale common mode input signal into a
differential mode input signal of 0.23ppm. When FO is
driven by an external oscillator with a frequency fEOSC,
every 1
mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 1.78 10–6 fEOSCppm. Figure 24
shows the typical offset error due to input common mode
voltage for various values of source resistance imbalance
between the IN+ and IN– pins when large CIN values are
used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
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