Figure 22. +FS Error vs RSOURCE
參數(shù)資料
型號: LTC2415IGN#TR
廠商: Linear Technology
文件頁數(shù): 22/40頁
文件大?。?/td> 0K
描述: IC A/D CONV 24BIT MICRPWR 16SSOP
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 24
采樣率(每秒): 15
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 1mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
其它名稱: LTC2415IGNTR
LTC2415/LTC2415-1
29
sn2415 24151fs
APPLICATIO S I FOR ATIO
WU
U
Figure 22. +FS Error vs RSOURCE at IN+ or IN(Large CIN)
Figure 23. –FS Error vs RSOURCE at IN+ or IN(Large CIN)
Figure 24. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN) and Input Source Resistance Imbalance
(
RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1F)
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+FS
ERROR
(ppm
OF
V
REF
)
2415 F22
300
240
180
120
60
0
VCC = 5V
REF+ = 5V
REF = GND
IN+ = 3.75V
IN= 1.25V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
FS
ERROR
(ppm
OF
V
REF
)
2415 F23
0
–60
–120
–180
–240
–300
VCC = 5V
REF+ = 5V
REF = GND
IN+ = 1.25V
IN= 3.75V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
VINCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
OFFSET
ERROR
(ppm
OF
V
REF
)
2415 F24
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
FO = GND
TA = 25°C
RSOURCEIN– = 500
CIN = 10F
VCC = 5V
REF+ = 5V
REF = GND
IN+ = IN= VINCM
A:
RIN = +400
B:
RIN = +200
C:
RIN = +100
D:
RIN = 0
E:
RIN = –100
F:
RIN = –200
G:
RIN = –400
A
B
C
D
E
F
G
used for the external source impedance seen by IN+ and
IN, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
V typical and 1V maximum offset voltage.
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