參數(shù)資料
型號(hào)： LTC2418IGN#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 24/48頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT DIFF INPUT 28SSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 16 個(gè)單端，單極；16 個(gè)單端，雙極；8 個(gè)差分，單極；8 個(gè)差分，雙極
配用： DC571A-ND - BOARD DELTA SIGMA ADC LTC2418
LTC2414/LTC2418
30
241418fa
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100
of source resistance driving REF+ or REF– translates
into about 1.34ppm additional INL error. When FO = HIGH
(internal oscillator and 50Hz notch), every 100
of source
resistance driving REF+ or REF– translates into about
1.1ppm additional INL error. When FO is driven by an
external oscillator with a frequency fEOSC, every 100 of
source resistance driving REF+ or REF– translates into
about 8.73 10–6 fEOSCppm additional INL error.
Figure 22 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF+
and REF– pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/
°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a onetime calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
±10nA max), results in a small gain error. A 100 source
resistance will create a 0.05
V typical and 0.5V maxi-
mum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2414/LTC2418
can produce up to 7.5 readings per second with a notch
frequency of 60Hz (FO = LOW) and 6.25 readings per
second with a notch frequency of 50Hz (FO = HIGH). The
actual output data rate will depend upon the length of the
sleep and data output phases which are controlled by the
user and which can be made insignificantly short. When
operated with an external conversion clock (FO connected
to an external oscillator), the LTC2414/LTC2418 output
data rate can be increased as desired up to that determined
by the maximum fEOSC frequency of 2000kHz. The dura-
tion of the conversion phase is 20510/fEOSC. If fEOSC =
153600Hz, the converter behaves as if the internal oscil-
lator is used and the notch is set at 60Hz. There is no
significant difference in the LTC2414/LTC2418 perfor-
mance between these two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent perfor-
mance degradation can be substantially reduced by rely-
ing upon the LTC2414/LTC2418’s exceptional common
APPLICATIO S I FOR ATIO
WU
UU
Figure 22. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF– for
Large CREF Values (CREF ≥ 1F)
VINDIF/VREFDIF
–0.5 –0.4–0.3–0.2–0.1 0
0.1 0.2 0.3 0.4 0.5
INL
(ppm
OF
V
REF
)
15
12
9
6
3
0
–3
–6
–9
–12
–15
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 0.5 (IN
+ + IN–) = 2.5V
FO = GND
CREF = 10F
TA = 25°C
RSOURCE = 1000
RSOURCE = 500
RSOURCE = 100
2414/18 F22
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