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參數(shù)資料
| 型號： | LTC2420 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Micropower 20-bit ADC(微功耗，20位串行模數(shù)轉換器) |
| 中文描述： | 微功耗20位ADC（微功耗，20位串行模數(shù)轉換器） |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 388K |
| 代理商： | LTC2420 |
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13
LTC2420
APPLICATIU
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 V
REF
to 1.125 V
REF
.
For input voltages
greater than 1.125 V
REF
, the conversion result is clamped
to the value corresponding to 1.125 V
REF
. For input
voltages below –0.125 V
REF
, the conversion result is
clamped to the value corresponding to –0.125 V
REF
.
W
U
U
Table 2. LTC2420 Output Data Format
Bit 23
EOC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 22
DMY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 21
SIG
1
1
1
1
1
1
1
1
1
1
1/0*
0
0
0
Bit 20
EXR
1
1
1
0
0
0
0
0
0
0
0
1
1
1
Bit 19
MSB
0
0
0
1
1
1
1
0
0
0
0
1
1
1
Bit 18
Bit 17
Bit 16
Bit 15
…
Bit 0
LSB
1
1
0
1
0
1
0
1
0
1
0
1
0
0
Input Voltage
V
IN
> 9/8 V
REF
9/8 V
REF
V
REF
+ 1LSB
V
REF
3/4V
REF
+ 1LSB
3/4V
REF
1/2V
REF
+ 1LSB
1/2V
REF
1/4V
REF
+ 1LSB
1/4V
REF
0
+
/0
–
–1LSB
–1/8 V
REF
V
IN
< –1/8 V
REF
*The sign bit changes state during the 0 code.
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
...
...
...
...
...
...
...
...
...
...
...
...
...
...
Frequency Rejection Selection (F
O
Pin Connection)
The LTC2420 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and its har-
monics for 50Hz
±
2% or 60Hz
±
2%. For 60Hz rejection, F
O
(Pin 8) should be connected to GND (Pin 4) while for 50Hz
rejection the F
O
pin should be connected to V
CC
(Pin1).
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2420 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the F
O
pin and turns off the internal oscillator. The
frequency f
EOSC
of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The exter-
nal clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2420 provides better than 110dB
normal mode rejection in a frequency range f
EOSC
/2560
±
4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from f
EOSC
/2560
is shown in Figure 5.
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