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| 型號： | LTC2424IG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 48-TSSOP -40 to 85 |
| 中文描述： | 4-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 409K |
| 代理商： | LTC2424IG |
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LTC2412
23
2412f
APPLICATIU
W
U
U
Parallel termination near the LTC2412 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27
and 56
placed near the
driver or near the LTC2412 pin will also eliminate this
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The multiple ground pins used
in this package configuration, as well as the differential
input and reference architecture, reduce substantially the
converter’s sensitivity to ground currents.
Particular attention must be given to the connection of the
F
O
signal when the LTC2412 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the F
O
signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
O
signal trace and the input/reference sig-
nals. When the F
O
signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the F
O
connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
O
signal as well as the loop area for
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2412 converter are
directly connected to a network of sampling capacitors.
Depending upon the relation between the differential input
voltage and the differential reference voltage, these ca-
pacitors are switching between these four pins transfering
small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 11, where IN
+
and IN
–
refer to the selected differential channel and the unselected
channel is omitted for simplicity.
V
REF
+
V
IN
+
V
CC
R
SW
(TYP)
20k
I
LEAK
I
LEAK
V
CC
V
CC
I
LEAK
I
LEAK
R
SW
(TYP)
20k
C
18pF
(TYP)
R
SW
(TYP)
20k
I
LEAK
I
IN
+
V
IN
–
I
IN
–
I
REF
+
I
REF
–
2412 F11
I
LEAK
V
CC
I
LEAK
I
LEAK
SWITCHING FREQUENCY
f
SW
= 76800Hz INTERNAL OSCILLATOR (F
O
= LOW OR HIGH)
f
SW
= 0.5 f
EOSC
EXTERNAL OSCILLATOR
V
REF
–
R
SW
(TYP)
20k
I IN
V
V
0 5
.
V
R
I IN
V
V
0 5
.
V
R
0 5
.
I REF
V
V
V
R
V
V
V
R
2
I REF
V
V
R
V
V
R
where
V
REF
AVG
IN
INCM
REFCM
EQ
AVG
)
IN
INCM
REFCM
EQ
AVG
)
REF
INCM
0 5
.
REFCM
EQ
IN
REF
EQ
AVG
REF
INCM
EQ
REFCM
IN
REF
EQ
+
+
)
)
=
+
=
+
=
+
=
+
+
1 5
.
1 5
.
2
:
=
.
.
.
/
REF
REF
+
V
REF
REF
V
IN
IN
+
V
IN
IN
R
R
M
M
INTERNAL OSCILLATOR
INTERNAL OSCILLATOR
)
Hz Notch F
Hz Notch F
50
LOW
HIGH
R
f
EXTERNAL OSCILLATOR
REFCM
IN
INCM
EQ
O
EQ
O
EQ
EOSC
=
+
2
=
=
2
=
=
=
=
(
(
)
)
=
(
+
+
3 61
4 32
0 555 10
12
60
Figure 11. LTC2412 Equivalent Analog Input Circuit
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