參數(shù)資料
型號(hào): LTC2440IGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 24-Bit High Speed Differential delta-sigma ADC with Selectable Speed/Resolution
中文描述: 1-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 4/28頁
文件大小: 316K
代理商: LTC2440IGN
LTC2440
4
sn2440, 2440fas
SYMBOL
V
CC
I
CC
PARAMETER
Supply Voltage
Supply Current
Conversion Mode
Sleep Mode
CONDITIONS
MIN
4.5
TYP
MAX
5.5
UNITS
V
CS = 0V (Note 7)
CS = V
CC
(Note 7)
8
8
11
30
mA
μ
A
The
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
°
C. (Note 3)
POWER REQUIRE E TS
SYMBOL
f
EOSC
t
HEO
t
LEO
t
CONV
PARAMETER
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
CONDITIONS
MIN
0.1
25
25
0.99
126
TYP
MAX
20
10000
10000
1.33
170
UNITS
MHz
ns
ns
ms
ms
OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
1.13
145
External Oscillator (Note 10, 13)
40 OSR + 170
f
EOSC
(kHz)
0.9
f
EOSC
/10
ms
f
ISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
(Note 9)
(Note 8)
(Note 8)
(Note 8)
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
(Note 8)
(Note 12)
(Note 12)
(Note 9)
(Notes 8, 12)
0.8
1
MHz
Hz
D
ISCK
f
ESCK
t
LESCK
t
HESCK
t
DOUT_ISCK
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 32-Bit Data Output Time
45
55
20
%
MHz
ns
ns
μ
s
25
25
41.6
35.3
30.9
320/f
EOSC
32/f
ESCK
s
s
t
DOUT_ESCK
t
1
t
2
t
3
t
4
t
KQMAX
t
KQMIN
t
5
t
7
t
8
External SCK 32-Bit Data Output Time
CS
to SDO Low Z
CS
to SDO High Z
CS
to SCK
CS
to SCK
SCK
to SDO Valid
SDO Hold After SCK
SCK Set-Up Before CS
SDI Setup Before SCK
SDI Hold After SCK
0
0
25
25
ns
ns
μ
s
ns
ns
ns
ns
ns
ns
5
25
25
(Note 5)
15
50
10
10
Note 5
Note 5
The
denotes specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (Note 3)
TI I G CHARACTERISTICS
W
U
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
V
CC
= 4.5 to 5.5V unless otherwise specified.
V
REF
= REF
+
– REF
, V
REFCM
= (REF
+
+ REF
)/2;
V
IN
= IN
+
– IN
, V
INCM
= (IN
+
+ IN
)/2.
Note 4:
F
O
pin tied to GND or to external conversion clock source with
f
EOSC
= 10MHz unless otherwise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7:
The converter uses the internal oscillator.
Note 8:
The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
ESCK
and is expressed in Hz.
Note 9:
The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of C
LOAD
= 20pF.
Note 10:
The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 11:
The converter uses the internal oscillator. F
O
= 0V.
Note 12:
Guaranteed by design and test correlation.
Note 13:
There is an internal reset that adds an additional 1
μ
s (typical) to
the conversion time.
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