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參數(shù)資料
型號(hào)： LTC2451ITS8#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 20/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT DELTA SIG TSOT23-8
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 60
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.2mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： SOT-23-8 薄型，TSOT-23-8
供應(yīng)商設(shè)備封裝： TSOT-23-8
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
配用： DC1383A-A-ND - BOARD DELTA SIGMA ADC LTC2451
LTC2451
9
2451fg
APPLICATIONS INFORMATION
VCC power should not be removed from the device when
the I2C bus is active to avoid loading the I2C bus lines
through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as
a transmitter or receiver, depending on the function of
the device. In addition to transmitters and receivers,
devices can also be considered as masters or slaves when
performing data transfers. A master is the device which
initiates a data transfer on the bus and generates the
clock signals to permit that transfer. Devices addressed
by the master are considered a slave. The address of the
LTC2451 is 0010100.
The LTC2451 can only be addressed as a slave. It can only
transmit the last conversion result. The serial clock line,
SCL, is always an input to the LTC2451 and the serial data
line, SDA, is bidirectional. Figure 2 shows the definition
of the I2C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is pulled
HIGH. The bus is free after a STOP is generated. START
and STOP conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr) is generated instead of a STOP condition. The re-
peated START (Sr) conditions are functionally identical
to the START (S).
Reference Voltage Range
Thisconverteracceptsatrulydifferentialexternalreference
voltage. The voltage range for the REF+ and REF– pins
covers the entire operating range of the device (GND to
VCC).Forcorrectconverteroperation,VREF+–VREF–≥2.5V.
The LTC2451 differential reference input range is 2.5V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND.
Input Voltage Range
Ignoring offset and full-scale errors, the converter will
theoretically output an “all zero” digital result when the
input is at VREF– (a zero scale input) and an “all one” digital
result when the input is at VREF+ (a full-scale input). In an
underrange condition, for all input voltages less than the
voltage corresponding to output code 0, the converter will
generate the output code 0. In an overrange condition,
for all input voltages greater than the voltage correspond-
ing to output code 65535, the converter will generate the
output code 65535.
I2C INTERFACE
The LTC2451 communicates through an I2C interface. The
I2C interface is a 2-wire open-drain interface supporting
multiple devices and masters on a single bus. The con-
nected devices can only pull the data line (SDA) LOW and
never drive it HIGH. SDA is externally connected to the
supply through a pull-up resistor. When the data line is
free, it is pulled HIGH through this resistor. Data on the
I2C bus can be transferred at rates up to 100k/s in the
standard mode and up to 400k/s in the fast mode. The
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
SDA
SCL
S
Sr
P
S
tHD(STA)
tHD(DAT)
tSU(STA)
tSU(STO)
tSU(DAT)
tLOW
tHD(SDA)
tSP
tBUF
tr
tf
tr
tf
tHIGH
2451 F02
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