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參數(shù)資料
| 型號： | LTC2480CDD |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 16-Bit ADC with Easy Drive |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | 3 X 3 MM, PLASTIC, MO-229WEED-2, DFN-10 |
| 文件頁數(shù)： | 25/40頁 |
| 文件大小： | 535K |
| 代理商： | LTC2480CDD |
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25
LTC2480
2480f
APPLICATIU
W
U
U
then immediately begins outputting data. The data input/
output cycle begins on the first rising edge of SCK and
ends after the 24th rising edge. The input data is then
shifted in via the SDI pin on the rising edge of SCK
(including the first rising edge) and the output data is
shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2480 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling,
PCB layout, antialiasing circuits, line frequency perturba-
tions and so on. Nevertheless, in order to preserve the
24-bit accuracy capability of this part, some simple pre-
cautions are required.
Digital Signal Levels
The LTC2480’s digital interface is easy to use. Its digital
inputs (SDI, F
O
, CS and SCK in External SCK mode of
operation) accept standard CMOS logic levels and the in-
ternal hysteresis receivers can tolerate edge transition times
as slow as 100
μ
s. However, some considerations are re-
quired to take advantage of the exceptional accuracy and
low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
CC
– 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, F
O
, CS
and SCK in External SCK mode of operation) is within
this range, the power supply current may increase even
if the signal in question is at a valid logic level. For
micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [V
IL
< 0.4V and
V
OH
> (V
CC
– 0.4V)].
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
EN
GS2
GS1
GS0
IM
FA
FB
SPD
SDI*
DON’T CARE
DON’T CARE
SDO
SCK
(INTERNAL)
CS
LSB
MSB
SIG
BIT 4
BIT 0
IM
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
DATA OUTPUT
CONVERSION
CONVERSION
2480 F10
V
CC
F
O
V
REF
IN
+
IN
–
SCK
SDI
SDO
CS
GND
2
10
INT/EXT CLOCK
3
4
5
9
7
8
6
1
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1
μ
F
2.7V TO 5.5V
LTC2480
3-WIRE
SPI INTERFACE
10k
V
CC
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