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參數(shù)資料
| 型號(hào)： | LTC2481CDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT I2C 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | I²C，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，雙極；1 個(gè)差分，雙極 |
| 配用： | DC951A-ND - BOARD DELTA SIGMA ADC LTC2481 |
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LTC2481
19
2481fc
APPLICATIONS INFORMATION
Easy Drive Input Current Cancellation
The LTC2481 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input
current. This enables external RC networks and high
impedance sensors to directly interface to the LTC2481
without external ampliers. The remaining common
mode input current is eliminated by either balancing the
differential input impedances or setting the common
mode input equal to the common mode reference (see
Automatic Input Current Cancellation section). This unique
architecture does not require on-chip buffers enabling
input signals to swing all the way to ground and up to
VCC. Furthermore, the cancellation does not interfere with
the transparent offset and full-scale auto-calibration and
the absolute accuracy (full-scale + offset + linearity) is
maintained even with external RC networks.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital lter
(commonly implemented as a SINC or Comb lter). For
high resolution, low frequency applications, this lter is
typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. The lter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2481 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
Frequency Rejection Selection (CA0/f0)
The LTC2481 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip conguration register (the default mode at power-
up is simultaneous 50Hz/60Hz rejection).
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2481 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the CA0/f0 pin and turns off the internal oscilla-
tor. The chip address for CA0 is internally set HIGH. The
frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not signicant as long as the minimum and maximum
specications for the high and low periods tHEO and tLEO
are observed.
Figure 8. Start a New Conversion without Reading Old Conversion Result
Figure 9. Synchronize the LTC2481s with the Global Address Call
7-BIT ADDRESS
CONVERSION
SLEEP
DATA INPUT
S
W ACK
WRITE (OPTIONAL)
P
2481 F08
GLOBAL ADDRESS
SCL
SDA
LTC2481
…
LTC2481
ALL LTC2481s IN SLEEP
CONVERSION OF ALL LTC2481s
DATA INPUT
S
W ACK
WRITE (OPTIONAL)
P
2481 F09
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