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參數(shù)資料
型號(hào)： LTC2481IDD#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 15/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT I2C 10-DFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 7.5
數(shù)據(jù)接口： I²C，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，雙極；1 個(gè)差分，雙極
配用： DC951A-ND - BOARD DELTA SIGMA ADC LTC2481
LTC2481
22
2481fc
APPLICATIONS INFORMATION
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2481 converts the bipolar differential
input signal, VIN = IN+ – IN–, from –FS to +FS where FS = 0.5
VREF/GAIN. Beyond this range, the converter indicates the
overrange or the underrange condition using distinct output
codes. Since the differential input current cancellation does
not rely on an on-chip buffer, current cancellation as well
as DC performance is maintained rail-to-rail.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance
of the devices. The effect of the series resistance on the
converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
Driving the Input and Reference
The input and reference pins of the LTC2481 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplied
equivalent circuit is shown in Figure 12.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see Fig-
ure 12), a rst order passive network with a time constant
τ = (RS + RSW) CEQ. The converter is able to sample the
input signal with better than 1ppm accuracy if the sampling
period is at least 14 times greater than the input circuit time
constant
τ. The sampling process on the four input analog
pins is quasi-independent so each time constant should be
considered by itself and, under worst-case circumstances,
the errors may add.
When using the internal oscillator, the LTC2481’s front-end
switched-capacitor network is clocked at 123kHz corre-
sponding to an 8.1μs sampling period. Thus, for settling
errors of less than 1ppm, the driving source impedance
should be chosen such that
τ≤8.1μs/14=580ns.Whenan
external oscillator of frequency fEOSC is used, the sampling
period is 2.5/fEOSC and, for a settling error of less than
1ppm,
τ ≤ 0.178/fEOSC.
VREF
+
VIN
+
VCC
RSW (TYP)
10k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
10k
CEQ
12pF
(TYP)
RSW (TYP)
10k
ILEAK
IIN
+
VIN
–
IIN
–
IREF
+
IREF
–
2481 F12
ILEAK
VCC
ILEAK
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 fEOSC EXTERNAL OSCILLATOR
VREF
–
RSW (TYP)
10k
IIN
I IN
VV
R
I REF
VV
V
R
V
VR
VD
R
VV
V
R
V
VR
where
AVG
IN CM
REF CM
EQ
AVG
REF
INCM
REFCM
EQ
IN
REF
EQ
REF
T
EQ
REF
REF CM
IN CM
EQ
IN
REF
EQ
REF
REF–
–
()
.
.–
.
–
05
15
05
15
05
2
:
.
V
VIN
IN
V
IN
R
MΩ INTERNAL OSCILLATOR
Hz MODE
REFCM
IN
INCM
EQ
V
, REF
REF
REF–
2
271
60
R
2.98MΩ INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
R
0.833 10
/ f
EXTERNAL OSCILLATOR
D IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
EQ
12
EOSC
T
WHERE REF– IS INTERNALLY TIED TO GND
Figure 12. LTC2481 Equivalent Analog Input Circuit
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