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參數(shù)資料
| 型號： | LTC2483CDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/34頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT I2C 10-DFN |
| 標準包裝： | 121 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC955A-ND - BOARD DELTA SIGMA ADC LTC2483 |
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LTC2483
2483fc
LTC2483 Data Format
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a read request
and 0 for a write request. If the 7-bit address agrees with
an LTC2483’s address, that device is selected. When the
device is in the conversion state, it does not accept the
request and issues a not-acknowledge (NACK) by leav-
ing SDA HIGH. A write operation will also generate an
NACK signal. If the conversion is complete, it issues an
acknowledge (ACK) by pulling SDA LOW.
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1A. When the LTC2483 is addressed for a
read operation, it acknowledges (by pulling SDA LOW)
and acts as a transmitter. The master and receiver can
read up to three bytes from the LTC2483. After a complete
read operation (3 bytes), the output register is emptied, a
new conversion is initiated, and a following read request
in the same output phase will be NACKed. The LTC2483
output data stream is 24 bits long, shifted out on the falling
edges of SCL. The first bit is the conversion result sign bit
(SIG), see Tables 1 and 2. This bit is HIGH if VIN ≥ 0. It is
LOW if VIN < 0. The second bit is the most significant bit
(MSB) of the result. The first two bits (SIG and MSB) can
applicaTions inFormaTion
be used to indicate over range conditions. If both bits are
HIGH, the differential input voltage is above +FS and the
following 16 bits are set to LOW to indicate an overrange
condition. If both bits are LOW, the input voltage is below
–FS and the following 16 bits are set to HIGH to indicate
an underrange condition. The function of these two bits
is summarized in Table 1. The next 16 bits contain the
conversion results in binary two’s complement format.
The remaining six bits are LOW.
As long as the voltage on the IN+ and IN– pins is main-
tained within the –0.3V to (VCC+0.3V)absolutemaximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1 LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1 LSB.
Table 1. LTC2483 Status Bits
INPUT RANGE
BIT 23
SIG
BIT 22
MSB
VIN ≥ 0.5 VREF
1
0V ≤ VIN < 0.5 VREF
1
0
–0.5 VREF ≤ VIN < 0V
0
1
VIN < –0.5 VREF
0
Table 2. LTC2483 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 23
SIG
BIT 22
MSB
BIT 21
BIT 20
BIT 19
…
BIT 6
VIN* ≥ FS**
1
0
…
0
FS** – 1 LSB
1
0
1
…
1
0.5 FS**
1
0
1
0
…
0
0.5 FS** – 1 LSB
1
0
1
…
1
0
1
0
…
0
–1 LSB
0
1
…
1
–0.5 FS**
0
1
0
…
0
–0.5 FS** – 1 LSB
0
1
0
1
…
1
–FS**
0
1
0
…
0
VIN* < –FS**
0
1
…
1
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 VREF.
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