verter with an I
參數(shù)資料
型號(hào)： LTC2483IDD#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 3/34頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT I2C 10-DFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)差分，雙極
配用： DC955A-ND - BOARD DELTA SIGMA ADC LTC2483
LTC2483
2483fc
CONVERTER OPERATION
Converter Operation Cycle
The LTC2483 is a low power, ∑ analog-to-digital con-
verter with an I2C interface. After power-on reset, its
operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1).
applicaTions inFormaTion
Figure 1. LTC2483 State Transition Diagram
CONVERSION
POWER-ON RESET
SLEEP
2483 F01
YES
NO
ACKNOWLEDGE
YES
NO
STOP
OR READ
24 BITS
DATA OUTPUT
Initially, the LTC2483 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read operation.
The conversion result is held indefinitely in a static shift
register while the converter is in the sleep state.
Thedevicewillnotacknowledgeanexternalrequestduring
the conversion state. After a conversion is finished, the
device is ready to accept a read request. Once the LTC2483
is addressed for a read operation, the device begins out-
putting the conversion result under control of the serial
clock (SCL). There is no latency in the conversion result.
The data output is 24 bits long and contains a 16-bit plus
sign conversion result. This result is shifted out on the
SDA pin under the control of the SCL. Data is updated
on the falling edges of SCL allowing the user to reliably
latch data on the rising edge of SCL. A new conversion is
initiated at the conclusion of a data read operation (read
out all 24 bits).
I2C INTERFACE
The LTC2483 communicates through an I2C interface.
The I2C interface is a 2-wire open-drain interface sup-
porting multiple devices and masters on a single bus.
The connected devices can only pull the bus wires LOW
and they never drive the bus HIGH. The bus wires are
externally connected to a positive supply voltage via a
current-source or pull-up resistor. When the bus is free,
both lines are HIGH. Data on the I2C bus can be transferred
at rates of up to 100kbit/s in the standard mode and up
to 400kbit/s in the fast mode. The VCC power should not
be removed from the device when the I2C bus is active to
avoid loading the I2C bus lines through the internal ESD
protection devices.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
canalsobeconsideredasmastersorslaveswhenperform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. At the same time any device ad-
dressed is considered a slave.
The LTC2483 can only be addressed as a slave. Once
addressed, it can transmit the last conversion result.
Therefore the serial clock line SCL is an input only and
the data line SDA is bidirectional (data out/address in).
The device supports the standard mode and the fast mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the definition of timing for fast/standard mode devices
on the I2C bus.
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