REF+ (Pin 1), REF–
參數(shù)資料
型號： LTC2483IDD#TRPBF
廠商： Linear Technology
文件頁數(shù)： 34/34頁
文件大?。?/td> 0K
描述： IC ADC 16BIT I2C 10-DFN
標準包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，雙極
配用： DC955A-ND - BOARD DELTA SIGMA ADC LTC2483
LTC2483
2483fc
pin FuncTions
REF+ (Pin 1), REF– (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input,
REF+, is more positive than the reference negative input,
REF–, by at least 0.1V.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 8) with a 1F tantalum capacitor in parallel with 0.1F
ceramic capacitor as close to the part as possible.
IN+(Pin4),IN–(Pin5):DifferentialAnalogInput.Thevolt-
age on these pins can have any value between GND – 0.3V
and VCC + 0.3V. Within these limits the converter bipolar
input range (VIN = IN+ – IN–) extends from –0.5 VREF to
0.5 VREF.Outsidethisinputrangetheconverterproduces
unique overrange and underrange output codes.
SCL (Pin 6): Serial Clock Pin of the I2C Interface. The
LTC2483 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted out the SDA
pin on the falling edges of the SCL clock.
SDA (Pin 7): Serial Data Output Line of the I2C Interface.
In the transmitter mode (read), the conversion result is
output through the SDA pin. It is an open-drain N-channel
driver and therefore an external pull-up resistor or current
source to VCC is needed.
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin
is configured as a three state (LOW, HIGH, or floating)
address control bit for the device I2C address.
CA0/F0 (Pin 10): Chip Address Control Pin/External Clock
Input Pin. When no transition is detected on the CA0/F0
pin, it is a two state (HIGH or floating) address control
bit for the device I2C address. When the pin is driven by
an external clock signal with a frequency fEOSC of at least
10kHz, the converter uses this signal as its system clock
and the fundamental digital filter rejection null is located
at a frequency fEOSC/5120 and sets the chip address CA0
internally to a HIGH.
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