參數(shù)資料
型號(hào)： LTC2484CDD#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 18/42頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 10-DFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 10-DFN（3x3）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
配用： DC939A-ND - BOARD DELTA SIGMA ADC LTC2484
LTC2484
25
2484fd
APPLICATIONS INFORMATION
Preserving the Converter Accuracy
The LTC2484 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling, PCB
layout, antialiasing circuits, line frequency perturbations
and so on. Nevertheless, in order to preserve the 24-bit
accuracy capability of this part, some simple precautions
are required.
Digital Signal Levels
The LTC2484’s digital interface is easy to use. Its digital
inputs (SDI, fO, CS and SCK in External SCK mode of
operation) accept standard CMOS logic levels and the
internal hysteresis receivers can tolerate edge transition
times as slow as 100μs. However, some considerations
are required to take advantage of the exceptional accuracy
and low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that, when
any one of the digital input signals (SDI, fO, CS and SCK in
External SCK mode of operation) is within this range, the
power supply current may increase even if the signal in
question is at a valid logic level. For micropower operation,
it is recommended to drive all digital input signals to full
CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch at the converter pin when the transition
time of an external control signal is less than twice the
propagation delay from the driver to the LTC2484. For
reference, on a regular FR-4 board, signal propagation
velocity is approximately 183ps/inch for internal traces
and 170ps/inch for surface traces. Thus, a driver gen-
erating a control signal with a minimum transition time
of 1ns must be connected to the converter pin through
a trace shorter than 2.5 inches. This problem becomes
particularly difcult when shared control lines are used
and multiple reections may occur. The solution is to
carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2484 pin will eliminate
this problem but will increase the driver power dissipa-
tion. A series resistor between 27Ω and 56Ω placed
near the driver output pin will also eliminate this problem
without additional power dissipation. The actual resistor
value depends upon the trace impedance and connection
topology.
An alternate solution is to reduce the edge rate of the control
signals. It should be noted that using very slow edges will
increase the converter power supply current during the
transition time. The differential input architecture reduces
the converter’s sensitivity to ground currents.
Particular attention must be given to the connection of
the fO signal when the LTC2484 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital lter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such pertur-
bations can occur due to asymmetric capacitive coupling
between the fO signal trace and the converter input and/or
reference connection traces. An immediate solution is to
maintain maximum possible separation between the fO
signal trace and the input/reference signals. When the fO
signal is parallel terminated near the converter, substantial
AC current is owing in the loop formed by the fO con-
nection trace, the termination and the ground return path.
Thus, perturbation signals may be inductively coupled into
the converter input and/or reference. In this situation, the
user must reduce to a minimum the loop area for the fO
signal as well as the loop area for the differential input
and reference connections. Even when fO is not driven,
other nearby signals pose similar EMI threats which will
be minimized by following good layout practices.
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