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| 型號(hào)： | LTC2485CDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 17/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT I2C 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | DC956A-ND - BOARD DELTA SIGMA ADC LTC2485 |
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LTC2485
24
2485fc
APPLICATIONS INFORMATION
Reference Current
In a similar fashion, the LTC2485 samples the differential
reference pins REF+ and REF– transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without signicant benets of reference
ltering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 1nF) may be
required as reference lters in certain congurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
resistanceis1MΩwhichgeneratesafull-scale(VREF/2)gain
error of 0.51ppm for each ohm of source resistance driving
the REF+ or REF– pins. For 50Hz/60Hz mode, the related
difference resistance is 1.1MΩ and the resulting full-scale
error is 0.46ppm for each ohm of source resistance driving
the REF+ and REF– pins. For 50Hz mode, the related differ-
ence resistance is 1.2MΩ and the resulting full-scale error
is 0.42ppm for each ohm of source resistance driving the
REF+ and REF– pins. When CA0/f0 is driven by an external
oscillator with a frequency fEOSC (external conversion clock
operation), the typical differential reference resistance is
0.30 1012/fEOSC Ω and each ohm of source resistance
driving the REF+ or REF– pins will result in 1.67 10–6
fEOSCppm gain error. The typical +FS and –FS errors for
various combinations of source resistance seen by the
REF+ or REF– pins and external capacitance connected to
that pin are shown in Figures 16-19.
In addition to this gain error, the converter INL per-
formance is degraded by the reference source imped-
ance. The INL is caused by the input dependent terms
–VIN2/(VREF REQ) – (0.5 VREF DT)/REQ in the reference
pin current as expressed in Figure 12. When using internal
oscillator and 60Hz mode, every 100Ω of reference source
resistance translates into about 0.67ppm additional INL
error. When using internal oscillator and 50Hz/60Hz mode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillator and 50Hz mode, every 100Ω of reference source
resistance translates into about 0.56ppm additional INL
error. When CA0/f0 is driven by an external oscillator
with a frequency fEOSC, every 100Ω of source resistance
driving REF+ or REF– translates into about 2.18 10–6
fEOSCppm additional INL error. Figure 20 shows the typical
INL error due to the source resistance driving the REF+
or REF– pins when large CREF values are used. The user
is advised to minimize the source impedance driving the
REF+ and REF– pins.
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (VREFCM – VINCM) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (VREFCM – VINCM)/(VREF REQ) full-scale gain error,
which is 0.074ppm when using internal oscillator and 60Hz
mode. When using internal oscillator and 50Hz/60Hz mode,
the extra full-scale gain error is 0.067ppm. When using
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 10–6 fEOSCppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specication can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by VREF+
and VREF–, the expected drift of the dynamic current gain
error will be insignicant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufcient.
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