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參數(shù)資料
| 型號(hào)： | LTC2485CDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 21/40頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT I2C 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | DC956A-ND - BOARD DELTA SIGMA ADC LTC2485 |
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LTC2485
28
2485fc
APPLICATIONS INFORMATION
Due to the complex ltering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a rst order lter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2485 input bandwidth is shown in
Figure 29. When an external oscillator of frequency fEOSC
is used, the shape of the LTC2485 input bandwidth can
be derived from Figure 29, 60Hz mode curve in which
the horizontal axis is scaled by fEOSC/307200.
The conversion noise (600nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an innite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplication circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplier stage followed by a
high bandwidth unity-gain buffer.
When external ampliers are driving the LTC2485, the
ADC input referred system noise calculation can be
simplied by Figure 30. The noise of an amplier driving
the LTC2485 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass lter with a
corner frequency fi. The amplier noise spectral density
is ni. From Figure 30, using fi as the x-axis selector, we
can nd on the y-axis the noise equivalent bandwidth freqi
of the input driving amplier. This bandwidth includes
the band limiting effects of the ADC internal calibration
and ltering. The noise of the driving amplier referred
to the converter input and including all these effects can
be calculated as N = ni √freqi. The total system noise
(referred to the LTC2485 input) can now be obtained by
summing as square root of sum of squares the three
ADC input referred noise sources: the LTC2485 internal
noise, the noise of the IN+ driving amplier and the noise
of the IN– driving amplier.
If the CA0/f0 pin is driven by an external oscillator of
frequency fEOSC, Figure 30 can still be used for noise
calculation if the x-axis is scaled by fEOSC/307200. For
large values of the ratio fEOSC/307200, the Figure 30 plot
accuracy begins to decrease, but at the same time the
LTC2485 noise oor rises and the noise contribution of
the driving ampliers lose signicance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ltering. Combined
with a large oversampling ratio, the LTC2485 signicantly
simplies antialiasing lter requirements. Additionally,
the input current cancellation feature of the LTC2485 al-
lows external lowpass ltering without degrading the DC
performance of the device.
The SINC4 digital lter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2485’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode
signal ltering both in the analog and digital domain.
Independent of the operating mode, fS = 256 fN = 2048
fOUTMAX where fN is the notch frequency and fOUTMAX
is the maximum output data rate. In the internal oscilla-
tor mode with a 50Hz notch setting, fS = 12800Hz, with
50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch
setting fS = 15360Hz. In the external oscillator mode, fS =
fEOSC/20. The performance of the normal mode rejection
is shown in Figures 31 and 32.
In 1x speed mode, the regions of low rejection occurring
at integer multiples of fS have a very narrow bandwidth.
Magnied details of the normal mode rejection curves
are shown in Figure 33 (rejection near DC) and Figure 34
(rejection at fS = 256fN) where fN represents the notch
frequency. These curves have been derived for the exter-
nal oscillator mode but they can be used in all operating
modes by appropriately selecting the fN value.
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