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參數(shù)資料
| 型號： | LTC2492IDE#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT DELTA SIG 14-DFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 配用： | DC1009A-A-ND - BOARD DELTA SIGMA ADC LTC2492 |
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LTC2492
18
2492fd
APPLICATIONS INFORMATION
conversion automatically begins at power up using this
default conguration. Once the conversion is complete,
a new word may be written into the device.
The rst three bits shifted into the device consist of two
preamble bits and an enable bit. These bits are used to
enable the device conguration and input channel selection.
Valid settings for these three bits are 000, 100 and 101.
Other combinations should be avoided. If the rst three bits
are 000 or 100, the following data is ignored (don’t care)
and the previously selected input channel and conguration
remain valid for the next conversion.
If the rst three bits shifted into the device are 101, then
the next ve bits select the input channel for the next
conversion cycle (see Table 3).
The rst input bit (SGL) following the 101 sequence
determines if the input selection is differential (SGL = 0)
or single-ended (SGL = 1). For SGL = 0, two adjacent
channels can be selected to form a differential input. For
SGL = 1, one of four channels is selected as the positive
input. The negative input is COM for all single-ended
operations. The remaining four bits (ODD, A2, A1, A0)
determine which channel(s) is/are selected and the polarity
(for a differential input).
The next serial input bit immediately following the input
channel selection is the enable bit for the conversion
conguration (EN2). If this bit is set to 0, then the next
conversion is performed using the previously selected
converter conguration.
A new conguration can be loaded into the device by
setting EN2 = 1 (see Table 4). The rst bit (IM) is used
to select the internal temperature sensor. If IM = 1, the
following conversion will be performed on the internal
temperature sensor rather than the selected input channel.
The next two bits (FA and FB) are used to set the rejection
frequency. The nal bit (SPD) is used to select either the
1x output rate if SPD = 0 (auto-calibration is enabled and
the offset is continuously calibrated and removed from
the nal conversion result) or the 2x output rate if SPD
= 1 (offset calibration disabled, multiplexing output rates
up to 15Hz with no latency). When IM = 1 (temperature
measurement) SPD will be ignored and the device will
operate in 1
× mode. The conguration remains valid until
Table 3 Channel Selection
MUX ADDRESS
CHANNEL SELECTION
SGL
ODD/
SIGN
A2
A1
A0
0
1
2
3
COM
*0
0000
IN+
IN–
00001
IN+
IN–
01000
IN–
IN+
01001
IN–
IN+
10000
IN+
IN–
10001
IN+
IN–
11000
IN+
IN–
11001
IN+
IN–
*Default at power up
Table 2. Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
BIT 31
EOC
BIT 30
DMY
BIT 29
SIG
BIT 28
MSB
BIT 27
BIT 26
BIT 25
…
BIT 5
LSB
BITS 4 to 0
SUB LSBs
VIN* ≥ 0.5 VREF**
0
1
0
…
0
00000
0.5 VREF** – 1LSB
0
1
0
1
…
1
XXXXX
0.25 VREF**
0
1
0
1
0
…
0
XXXXX
0.25 VREF** – 1LSB
0
1/0
0
1
…
1
XXXXX
0
1
0
…
0
XXXXX
–1LSB
0
1
…
1
XXXXX
–0.25 VREF**
0
1
0
…
0
XXXXX
–0.25 VREF** – 1LSB
0
1
0
1
…
1
XXXXX
–0.5 VREF**
0
1
0
…
0
XXXXX
VIN* < –0.5 VREF**
0
1
…
1
11111
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–. Sub LSBs are below the 24-bit level. They may be included in averaging, or discarded without loss of resolution.
The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
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