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參數(shù)資料
| 型號： | LTC2492IDE#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/36頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT DELTA SIG 14-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 14-DFN-EP（4x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 配用： | DC1009A-A-ND - BOARD DELTA SIGMA ADC LTC2492 |
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LTC2492
23
2492fd
VCC
fO
SCK
SDI
GND
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2492
3-WIRE
SPI INTERFACE
EOC
CS
SCK
(EXTERNAL)
SDI
SDO
2492 F08
CONVERSION
SLEEP
DATA INPUT/OUTPUT
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21
BIT 20 BIT 19
BIT 29
BIT 30
BIT 31
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
ODD
BIT 18 BIT 17
BIT 0
12
3
4
5
6
7
8
9
10
11
12
13
14
32
DON'T CARE
MSB
SIG
“0”
REF+
REF–
CH0
CH1
CH2
CH3
COM
SDO
12
1
13
14
8
9
10
11
7
3
5
6
4
2
2.7V TO 5.5V
0.1μF
10μF
CS
CONVERSION
APPLICATIONS INFORMATION
Figure 8. External Serial Clock, 3-Wire Operation (
`C`S = 0)
On the falling edge of EOC, the conversion result is
loading into an internal static shift register. The output
data can now be shifted out the SDO pin under control
of the externally applied SCK signal. Data is updated on
the falling edge of SCK. The input data is shifted into the
device through the SDI pin on the rising edge of SCK. On
the 32nd falling edge of SCK, SDO goes HIGH, indicating
a new conversion has begun. This data now serves as
EOC for the next conversion.
Internal Serial Clock, Single Cycle Operation
This timing mode uses the internal serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 9).
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be oating or pulled HIGH
before the conclusion of the POR cycle and prior to each
falling edge of CS. An internal weak pull-up resistor is active
on the SCK pin during the falling edge of CS; therefore,
the internal SCK mode is automatically selected if SCK is
not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while the conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete
(EOC = 0), the device will exit sleep state. In order to return
to the sleep state and reduce the power consumption, CS
must be pulled HIGH before the device pulls SCK HIGH.
When the device is using its own internal oscillator (fO
is tied LOW), the rst rising edge of SCK occurs 12μs
(tEOCTEST = 12μs) after the falling edge of CS. If fO is
driven by an external oscillator of frequency fEOSC, then
tEOCTEST = 3.6/fEOSC.
If CS remains LOW longer than tEOCTEST, the rst rising
edge of SCK will occur and the conversion result is shifted
out the SDO pin on the falling edge of SCK. The serial
input word (SDI) is shifted into the device on the rising
edge of SCK.
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