參數(shù)資料
型號(hào)： LTC2498IUHF#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 3/38頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 16CH 38-QFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 38-QFN（5x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 16 個(gè)單端，雙極；8 個(gè)差分，雙極
配用： DC1011A-A-ND - BOARD DELTA SIGMA ADC LTC2498
LTC2498
11
2498ff
pin Functions
SDI(Pin34):SerialDataInput.Thispinisusedtoselectthe
linefrequencyrejectionmode,1xor2xmode,temperature
sensor, as well as the input channel. The serial data input
is applied under control of the serial clock (SCK) during
the data output/input operation. The first conversion fol-
lowing a new input or mode change is valid.
fO (Pin 35): Frequency Control Pin. Digital input that
controls the internal conversion clock rate. When fO is
connected to VCC or GND, the converter uses its internal
oscillator running at 307.2kHz. The conversion clock may
also be overridden by driving the fO pin with an external
clock in order to change the output rate and the digital
filter rejection null.
CS (Pin 36): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output aborts the data transfer and starts
a new conversion.
SDO (Pin 37): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select pin is HIGH, the SDO pin is in a high
impedancestate.Duringtheconversionandsleepperiods,
this pin is used as the conversion status output. When
the conversion is in progress this pin is HIGH; once the
conversion is complete SDO goes LOW. The conversion
status is monitored by pulling CS LOW.
SCK(Pin38):Bidirectional,DigitalI/O,ClockPin.InInternal
Serial Clock Operation mode, SCK is generated internally
and is seen as an output on the SCK pin . In External Serial
Clock Operation mode, the digital I/O clock is externally
applied to the SCK pin. The Serial Clock operation mode
is determined by the logic level applied to the SCK pin at
power-up and during the most recent falling edge of CS.
Exposed Pad (Pin 39): Ground. This pin is ground and
mustbesolderedtothePCBgroundplane.Forprototyping
purposes, this pin may remain floating.
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