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參數(shù)資料
| 型號： | LTC2641IMS8-16#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT VOUT 8-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Open Loop DAC |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時間： | 1µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 600µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1352 (CN2011-ZH PDF) |
LTC2641/LTC2642
9
26412fc
For more information www.linear.com/LTC2641
pin FuncTions
LTC2641 – MSOP, DFN Packages
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
CS (Pin 2): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 4): Serial Interface Data Input. Data is applied
to DIN for transfer to the device at the rising edge of
SCLK.
CLR (Pin 5): Asynchronous Clear Input. A logic low clears
the DAC to code 0.
VOUT (Pin 6): DAC Output Voltage. The output range is
0V to VREF.
VDD (Pin 7): Supply Voltage. Set between 2.7V and
5.5V.
GND (Pin 8): Circuit Ground.
Exposed Pad (DFN Pin 9): Circuit Ground. Must be sol-
dered to PCB ground.
LTC2641 – SO Package OBSOLETE
VOUT (Pin 1): DAC Output Voltage. The output range is
0V to VREF.
GND (Pin 2): Circuit Ground.
REF (Pin 3): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
CS (Pin 4): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
SCLK (Pin 5): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 6): Serial Interface Data Input. Data is applied
to DIN for transfer to the device at the rising edge of
SCLK.
GND (Pin 7): Circuit Ground Pin. Must be connected to
Pin 2 (GND).
VDD (Pin 8): Supply Voltage. Set between 2.7V and
5.5V.
LTC2642 – MSOP, DFN Packages
REF (Pin 1): Reference Voltage Input. Apply an external
reference at REF between 2V and VDD.
CS (Pin 2): Serial Interface Chip Select/Load Input. When
CS is low, SCLK is enabled for shifting in data on DIN.
When CS is taken high, SCLK is disabled, the 16-bit input
word is latched and the DAC is updated.
SCLK (Pin 3): Serial Interface Clock Input. CMOS and
TTL compatible.
DIN (Pin 4): Serial Interface Data Input. Data is applied
to DIN for transfer to the device at the rising edge of
SCLK.
CLR (Pin 5): Asynchronous Clear Input. A logic low clears
the DAC to midscale.
VOUT (Pin 6): DAC Output Voltage. The output range is
0V to VREF.
INV (Pin 7): Center Tap of Internal Scaling Resistors. Con-
nect to an external amplifier’s inverting input in bipolar
mode.
RFB (Pin 8): Feedback Resistor. Connect to an external
amplifier’s output in bipolar mode. The bipolar output
range is –VREF to VREF.
VDD (Pin 9): Supply Voltage. Set between 2.7V and
5.5V.
GND (Pin 10): Circuit Ground.
Exposed Pad (DFN Pin 11): Circuit Ground. Must be
soldered to PCB ground.
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