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參數(shù)資料
| 型號： | LTC2751IUHF-14#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/22頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT CUR OUT 38-QFN |
| 產(chǎn)品培訓模塊： | LTC275x 18-Bit DAC |
| 標準包裝： | 2,500 |
| 系列： | SoftSpan™ |
| 設置時間： | 2µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 38-QFN（5x7） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | * |
LTC2751
14
2751fa
operaTion
isatwo-functionpin.Theupdatefunctionisdisabledwhen
READ is high, and the UPD pin instead selects the input
or DAC register for readback. Table 1 shows the readback
functions for the LTC2751.
The most common readback task is to check the contents
of an input register after writing to it, before updating the
new data to the DAC register. To do this, bring READ high
while holding UPD low. The contents of the selected port’s
input register are output by the data or span I/O pins.
To read back the contents of a DAC register, bring READ
high, then bring UPD high. The contents of the selected
data or span DAC register are output by the data or span
I/O pins. Note: if no update is desired after the readback
operation, UPD must be returned low before bringing
READ low, otherwise the UPD pin will revert to its primary
function and update the DAC.
System Offset Adjustment
Many systems require compensation for overall system
offset. The RVOS offset adjustment pin is provided for this
purpose. For noise immunity and ease of adjustment, the
control voltage is attenuated to the DAC output:
VOS = –0.01 V(RVOS) [0V to 5V, ±2.5V spans]
VOS = –0.02 V(RVOS) [0V to 10V, ±5V,
–2.5V to 7.5V spans]
VOS = –0.04 V(RVOS) [±10V span]
The nominal input range of this pin is ±5V; other refer-
ence voltages of up to ±15V may be used if needed. The
RVOS pin has an input impedance of 1MW. To preserve the
settling performance of the LTC2751, this pin should be
driven with a Thevenin-equivalent impedance of 10k
W or
less. If not used, RVOS should be shorted to IOUT2.
Table 2. Span Codes
S2
S1
S0
SPAN
0
Unipolar 0V to 5V
0
1
Unipolar 0V to 10V
0
1
0
Bipolar –5V to 5V
0
1
Bipolar –10V to 10V
1
0
Bipolar –2.5V to 2.5V
1
0
1
Bipolar –2.5V to 7.5V
Codes not shown are reserved and should not be used.
Readback
The contents of any one of the four interface registers can
be read back by using the READ pin in conjunction with
the D/S and UPD pins.
A readback operation is initiated by bringing READ to logic
high.TheI/Opins,whicharehigh-impedancedigitalinputs
when READ is low, selectively change to low-impedance
logic outputs during readback.
The I/O pins comprise two ports, data and span. The data
I/O port consists of pins D0-D11, D0-D13 or D0-D15
(LTC2751-12, LTC2751-14 or LTC2751-16, respectively).
The span I/O port consists of pins S0, S1 and S2 for all
parts.
Each I/O port has one dedicated input register and one
dedicated DAC register. The register structure is shown
in the Block Diagram.
The D/S pin is used to select which I/O port (data or span)
isconfiguredtoreadbackthecontentsofitsregisters. The
unselected I/O port’s pins remain high-impedance inputs.
Once the I/O port is selected, its input or DAC register is
selected for readback by using the UPD pin. Note that UPD
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