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參數(shù)資料
| 型號： | LTC2753IUK-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT DUAL 48-QFN |
| 標準包裝： | 52 |
| 系列： | SoftSpan™ |
| 設置時間： | 2µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | * |
LTC2753
10
2753f
PIN FUNCTIONS
RCOM (Pin 1): Center Tap Point for the Reference Inverting
Resistors. The 20k reference inverting resistors R1 and R2
are connected internally from RIN to RCOM and from RCOM
to REFA, respectively (see Block Diagram). For normal
operation tie RCOM to the negative input of the external
reference inverting amplier (see Typical Applications).
RIN (Pin 2): Input Resistor R1 of the Reference Inverting
Resistors. The 20k resistor R1 is connected internally from
RIN to RCOM. For normal operation tie RIN to the external
reference voltage VREF. Typically 5V; accepts up to ±15V.
S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used
to program and to read back the output ranges of the
DACs.
IOUT2A (Pin 4): DAC A Current Output Complement. Tie
IOUT2A to ground.
GND (Pin 5): Shield Ground, provides necessary shielding
for IOUT2A. Tie to ground.
D3-D11 (Pins 6-14): LTC2753-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D11 is the MSB.
D5-D13 (Pins 6-14): LTC2753-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D13 is the MSB.
D7-D15 (Pins 6-14): LTC2753-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D15 is the MSB.
VDD (Pin 15): Positive Supply Input 2.7V ≤ VDD ≤ 5.5V.
Requires a 0.1μF bypass capacitor to GND.
NC (Pin 16): No Internal Connection.
A1 (Pin 17): DAC Address Bit 1. See Table 3.
A0 (Pin 18): DAC Address Bit 0. See Table 3.
GND (Pin 19): Ground. Tie to ground.
CLR (Pin 20): Asynchronous Clear. When CLR is taken
to a logic low, the data registers are reset to the zero-volt
code for the present output range (VOUT = 0V).
MSPAN (Pin 21): Manual Span Control Pin. MSPAN is used
to congure the LTC2753 for operation in a single, xed
output range. When congured for single-span operation,
the output range is set via hardware pin strapping. The
input and DAC registers of the span I/O port are transparent
and do not respond to write or update commands.
To congure the part for single-span use, tie MSPAN directly
to VDD. If MSPAN is instead connected to GND (SoftSpan
conguration), the output ranges are set and veried by
using write, update and read operations. See Manual Span
Conguration in the Operation section. MSPAN must be
connected either directly to GND (SoftSpan conguration)
or VDD (single-span conguration).
D0-D2 (Pins 22-24): LTC2753-12 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
D0-D4 (Pins 22-26): LTC2753-14 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
D0-D6 (Pins 22-28): LTC2753-16 Only. DAC Input/Output
Data Bits. These I/O pins set and read back the DAC code.
D0 is the LSB.
NC (Pins 25-30): LTC2753-12 Only. No Internal Connection.
NC (Pins 27-30): LTC2753-14 Only. No Internal Connection.
NC (Pins 29, 30): LTC2753-16 Only. No Internal Con-
nection.
GND (Pin 31): Shield Ground, provides necessary shielding
for IOUT2B. Tie to ground.
IOUT2B (Pin 32): DAC B Current Output Complement. Tie
IOUT2B to ground.
S0 (Pin 33): Span I/O Bit 0. Pins S0, S1 and S2 are used to
program and to read back the output range of the DACs.
D/S (Pin 34): Data/Span Select. This pin is used to select
the data I/O pins or the span I/O pins (D0 to D15 or S0
to S2, respectively), along with their respective dedicated
registers, for write or read operations. Update operations
ignore D/S, since all updates affect both data and span
registers. For single-span operation, tie D/S to ground.
READ (Pin 35): Read Pin. When READ is asserted high,
the data I/O pins (D0-D15) or span I/O pins (S0-S2)
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