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參數(shù)資料
| 型號(hào)： | LTC2753IUK-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT DUAL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 52 |
| 系列： | SoftSpan™ |
| 設(shè)置時(shí)間： | 2µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN-EP（7x7） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | * |
LTC2753
15
2753f
OPERATION
the D/S pin. The selected I/O port’s pins become logic
outputs during readback, while the unselected I/O port’s
pins remain high-impedance inputs.
With the DAC channel and I/O port selected, assert READ
high and select the desired input or DAC register using the
UPD pin. Note that UPD is a two function pin—the update
function is only available when READ is low. When READ
is high, the update function is disabled and the UPD pin
instead selects the input or DAC register for readback.
Table 1 shows the readback functions for the LTC2753.
Table 1. Write, Update and Read Functions
READ D/S
WR UPD
SPAN I/O
DATA I/O
0
-
Write to Input Register
0
1
-
Write/Update
(Transparent)
00
1
0
-
0
1
Update DAC Register
0
1
0
Write to Input Register
-
0
1
0
1
Write/Update
(Transparent)
-
01
1
0
-
0
1
Update DAC register
Update DAC Register
1
0
X
0
-
Read Input Register
1
0
X
1
-
Read DAC Register
1
X
0
Read Input Register
-
1
X
1
Read DAC Register
-
X = Don’t Care
The most common readback task is to check the contents
of an input register after writing to it, before updating the
new data to the DAC register. To do this, hold UPD low
and assert READ high. The contents of the selected port’s
input register are output to its I/O pins.
To read back the contents of a DAC register, hold UPD low
and assert READ high, then bring UPD high to select the
DAC register. The contents of the selected DAC register are
output by the selected port’s I/O pins. Note: if no update is
desired after the readback operation, UPD must be returned
low before bringing READ low; otherwise the UPD pin will
revert to its primary function and update the DAC.
These devices also have a power-on reset that initializes
both DACs to VOUT = 0V in any output range. The DACs
power up in the 0V-5V range if the part is in SoftSpan
conguration; for manual span (see Manual Span Congu-
ration below), both DACs power up in the manually-chosen
range at the appropriate code.
Manual Span Conguration
Multiple output ranges are not needed in some applications.
To congure the LTC2753 for single-span operation, tie the
MSPAN pin to VDD and the D/S pin to GND. The desired
output range is then specied by the span I/O pins (S0,
S1 and S2) as usual, but the pins are programmed by ty-
ing directly to GND or VDD (see Figure 1 and Table 2). In
this conguration, both DAC channels will initialize to the
chosen output range at power-up, with VOUT = 0V.
When congured for manual span operation, span pin
readback is disabled.
Readback
The contents of any one of the 8 interface registers can
be read back from the I/O ports.
The I/O pins are grouped into two ports: data and span. The
data I/O port comprises pins D0-D11, D0-D13 or D0-D15
(LTC2753-12, LTC2753-14 or LTC2753-16, respectively).
The span I/O port comprises pins S0, S1 and S2 for all
parts.
Each DAC channel has a set of data registers that are
controlled and read back from the data I/O port; and a set
of span registers that are controlled and read back from
the span I/O port. The register structure is shown in the
Block Diagram.
A readback operation is initiated by asserting READ to
logic high after selecting the desired DAC channel and I/O
port. The I/O pins, which are high-impedance digital inputs
when READ is low, selectively change to low-impedance
logic outputs during readback.
Select the DAC channel with address pins A1 and A0, and
select the I/O port (data or span) to be read back with
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