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參數(shù)資料
型號(hào)： LTC2754ACUKG-16#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 2/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT QUAD IOUT 52-QFN
標(biāo)準(zhǔn)包裝： 2,000
系列： SoftSpan™
設(shè)置時(shí)間： 2µs
位數(shù)： 16
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 52-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 52-QFN（7x8）裸露焊盤
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 8 電流，單極；8 電流，雙極
采樣率（每秒）： *
配用： DC1546A-ND - BOARD DAC LTC2754-16
LTC2754
10
2754f
S0 (Pin 33): Span Bit 0. In Manual Span mode (M-SPAN
tied to VDD), Pins S0, S1 and S2 are pin-strapped to select
a single xed output range for all DACs. These pins should
be tied to either GND or VDD even if they are unused.
S1 (Pin 34): Span Bit 1. In Manual Span mode (M-SPAN
tied to VDD), Pins S0, S1 and S2 are pin-strapped to select
a single xed output range for all DACs. These pins should
be tied to either GND or VDD even if they are unused.
S2 (Pin 35): Span Bit 2. In Manual Span mode (M-SPAN
tied to VDD), Pins S0, S1 and S2 are pin-strapped to select
a single xed output range for all DACs. These pins should
be tied to either GND or VDD even if they are unused.
LDAC (Pin 36): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated (CS/LD must
be high).
GND (Pin 37): Ground; provides shielding for IOUT2B. Tie
to ground.
IOUT2B (Pin 38): DAC B Current Output Complement. Tie
IOUT2B to ground.
RINB (Pin 39): Input Resistor for Reference Inverting
Amplier. The 20k input resistor is connected internally
from RINB to RCOMB. For normal operation tie RINB to the
external reference voltage VREFB (see Typical Applica-
tions). Any or all of these precision-matched resistor sets
(Each set comprising RINX, RCOMX and REFX) may be
used to invert one or more positive reference voltages to
the negative voltages needed by the DACs. Typically 5V;
accepts up to ±15V.
GEADJB (Pin 40): Gain Adjust Pin for DAC B. This control
pin can be used to null gain error or to compensate for
reference errors. Nominal adjustment range is ±512 LSB
(LTC2754-16) for a voltage input range of ±VRINB (i.e., ±5V
for a 5V reference input). Tie to ground if not used.
RCOMB (Pin 41): Center Tap Point for Reference Amplier
Inverting Resistors. The 20k reference inverting resistors
are connected internally from RINB to RCOMB and from
RCOMB to REFB, respectively (see Block Diagram). For
normal operation tie RCOMB tothenegativeinputofexternal
reference inverting amplier (see Typical Applications).
REFB (Pin 42): Inverted Reference Voltage for DAC B, with
internal connection to the reference inverting resistor. The
20k resistor is connected internally from REFB to RCOMB.
For normal operation tie this pin to the output of reference
inverting amplier (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (RINB and RCOMB oating).
ROFSB (Pin 43): Bipolar Offset Network for DAC B. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RINB (Pin 39). The
impedance looking into this pin is 20k to ground.
RFBB (Pin 44): DAC B Feedback Resistor. For normal
operation tie to the output of the I/V converter amplier
for DAC B (see Typical Applications). The DAC output
current from IOUT1B ows through the feedback resistor
to the RFBB pin. The impedance looking into this pin is
10k to ground.
IOUT1B (Pin 45): DAC B Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplier for DAC B (see Typical Applications).
VOSADJB (Pin 46): DAC B Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset-voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJB produces ΔVOS =
–512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RINB). Tie to ground if not used.
VOSADJA (Pin 47): DAC A Offset Adjust Pin. This control
pin can be used to null unipolar offset or bipolar zero error.
The offset-voltage delta is inverted and attenuated such that
a 5V control voltage applied to VOSADJA produces ΔVOS =
–512 LSB (LTC2754-16) in any output range (assumes a
5V reference voltage at RINA). Tie to ground if not used.
IOUT1A (Pin 48): DAC A Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplier for DAC A (see Typical Applications).
RFBA (Pin 49): DAC A Feedback Resistor. For normal
operation tie to the output of the I/V converter amplier
for DAC A (see Typical Applications). The DAC output
current from IOUT1A ows through the feedback resistor
to the RFBA pin. The impedance looking into this pin is
10k to ground.
PIN FUNCTIONS
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