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參數(shù)資料
| 型號： | LTC2758BILX#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 18BIT SPI/SRL 48-LQFP |
| 標準包裝： | 250 |
| 系列： | SoftSpan™ |
| 設置時間： | 2.1µs |
| 位數(shù)： | 18 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；4 電流，雙極 |
| 配用： | DC1684A-A-ND - BOARD DAC LTC2758 |
LTC2758
15
2758fa
For more information www.linear.com/LTC2758
System Offset and Reference Adjustments
Many systems require compensation for overall system
offset. This may be an order of magnitude or more greater
than the offset of the LTC2758, which is so low as to be
dominated by external output amplifier errors even when
using the most precise op amps.
The offset adjust pins VOSADJX can be used to null unipolar
offset or bipolar zero error. The offset change expressed
in LSB is the same for any output range:
VOS LSB
[ ]= –V(VOSADJX)
V(RINX)
2048
A 5V control voltage applied to VOSADJX produces VOS =
–2048 LSB in any output range, assuming a 5V reference
voltage at RINX.
In voltage terms, the offset delta is attenuated by a factor
of 32, 64 or 128, depending on the output range. (These
functions hold regardless of reference voltage.)
VOS = –(1/128)VOSADJX
[0V to 5V, ±2.5V spans]
VOS = –(1/64)VOSADJX
[0V to 10V, ±5V, –2.5V to
7.5V spans]
VOS = –(1/32)VOSADJX
[±10V span]
The gain error adjust pins GEADJX can be used to null
gain error or to compensate for reference errors. The
gain error change expressed in LSB is the same for any
output range:
GE =
V(GEADJX)
V(RINX)
2048
The gain-error delta is non-inverting for positive reference
voltages.
Note that this pin compensates the gain by altering the
inverted reference voltage V(REFX). In voltage terms, the
V(REFX) delta is inverted and attenuated by a factor of
128.
V(REFX) = –(1/128)GEADJX
The nominal input range of these pins is ±5V; other volt-
ages of up to ±15V may be used if needed. However, do
OPERATION
not use voltages divided down from power supplies; ref-
erence-quality, low-noise inputs are required to maintain
the best DAC performance.
The VOSADJX pins have an input impedance of 1.28MΩ.
These pins should be driven with a Thevenin-equivalent
impedance of 10k or less to preserve the settling perfor-
mance of the LTC2758. They should be shorted to GND
if not used.
The GEADJX pins have an input impedance of 2.56MΩ, and
are intended for use with fixed reference voltages only.
They should be shorted to GND if not used.
Power-On Reset and Clear
When power is first applied to the LTC2758, all DACs
power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
initialize to zero volts.
If the part is configured for manual span operation, all
DACs will be set into the pin-strapped range at the first
Update command. This allows the user to simultaneously
update span and code for a smooth voltage transition into
the chosen output range.
When the CLR pin is taken low, a system clear results.
The DAC buffers are reset to 0 and the DAC outputs are
all reset to zero volts. The Input buffers are left intact, so
that any subsequent Update command (including the use
of LDAC) restores the addressed DACs to their respective
previous states.
If CLR is asserted during an instruction, i.e., when CS/LD
is low, the instruction is aborted. Integrity of the relevant
Input buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the supply VDD dips below
approximately2V;andstaysasserteduntilanyvalidUpdate
command is executed.
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