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參數(shù)資料
| 型號： | LTC3537EUD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 314K |
| 描述： | IC REG DL BST/LINEAR SYNC 16-QFN |
| 標準包裝： | 2,500 |
| 拓撲： | 升壓（升壓）同步（1），線性（LDO）（1） |
| 功能： | 任何功能 |
| 輸出數(shù)： | 2 |
| 頻率 - 開關(guān)： | 2.2MHz |
| 電壓/電流 - 輸出 1： | 1.5 V ~ 5.25 V，100mA |
| 電壓/電流 - 輸出 2： | 0.6 V ~ 5 V，100mA |
| 帶 LED 驅(qū)動器： | 無 |
| 帶監(jiān)控器： | 無 |
| 帶序列發(fā)生器： | 是 |
| 電源電壓： | 0.68 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 16-QFN-EP（3x3） |
| 包裝： | 帶卷 (TR) |
LTC3537
9
3537fd
PIN FUNCTIONS
MODE (Pin 1): Logic Controlled Input for the Auto-Burst
Mode Feature.
MODE = High: PWM operation with Burst Mode
Operation
MODE = Low: PWM operation only
LBI (Pin 2): Low-Battery Comparator Non-Inverting Input.
(Comparator enabled with ENBST or ENLDO)
SGND (Pin 3): Signal Ground. Provide a short direct PCB
path between GND and the () side of the input and output
capacitors.
V
INB
(Pin 4): Input Supply for the Step-Up Converter.
Connect a minimum of 1糉 ceramic decoupling capacitor
from this pin to ground.
PGDB (Pin 5): Power Good Indicator for the Boost Con-
verter. This is an open-drain output that sinks current
when V
OUTB
is less than 94% of the programmed voltage.
ENBST (Pin 6): Logic controlled shutdown input for the
boost converter.
ENBST = High: Normal operation
ENBST = Low: Shutdown
PGDL (Pin 7): Power Good Indicator for the LDO Regula-
tor. This is an open-drain output that sinks current when
V
OLDO
is less than 96% of the programmed voltage.
ENLDO (Pin 8): Logic Controlled Shutdown Input for the
LDO Regulator.
ENLDO = High: Normal operation
ENLDO = Low: Shutdown
FBB (Pin 9): Feedback Input to the g
m
Error Ampli er
of the Boost Converter. Connect resistor divider tap to
this pin. The output voltage can be adjusted from 1.5V
to 5.25V by:
V
OUTB
= 1.21V " [1 + (R2/R1)]
FBL (Pin 10): Feedback Input to the g
m
Error Ampli er of
the LDO. Connect resistor divider tap to this pin. The output
voltage can be adjusted from 0.6V (typical) to 5V by:
V
OLDO
= 0.6V " [1 + (R4/R3)]
V
OLDO
(Pin 11): LDO Regulator Output. PCB trace from
V
OLDO
to the output lter capacitor (1糉 minimum) should
be as short and as wide as possible.
V
INL
(Pin 12): Input Supply for the LDO Regulator.
V
OUTB
(Pin 13): Output Voltage Sense Input and Drain
of the Internal Synchronous Recti er. PCB trace length
from V
OUTB
to the output lter capacitor (4.7糉 minimum)
should be as short and wide as possible.
SW (Pin 14): Switch Pin. Connect the inductor between
SW and V
INB
. Keep these PCB trace lengths as short and
wide as possible to reduce EMI. If the inductor current falls
to zero or ENBST is low, an internal anti-ringing switch is
connected from SW to V
INB
to minimize EMI.
PGND (Pin 15): Power Ground. Provide a short direct
PCB path between GND and the () side of the input and
output capacitors.
LBO (Pin 16): Low-Battery Comparator Output. (Open-
Drain)
GND (Exposed Pad Pin 17): Power Ground. The Exposed
Pad must be soldered to the PCB.
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