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參數(shù)資料
| 型號： | LTC3711 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 4A, High Efficiency, Standalone Li Battery Charger |
| 中文描述： | 第4A，高效，獨立鋰電池充電器 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 241K |
| 代理商： | LTC3711 |
17
LTC4007
4007i
APPLICATIU
Example #2: 100k
NTC
TLOW = 5
°
C, THIGH = 50
°
C
R
TH
= 100k at 25
°
C,
R
TH(LOW)
= 272.05k at 5
°
C
R
TH(HIGH)
= 33.195k at 50
°
C
R9 = 226.9k
→
226k (nearest 1% value)
R9A = 1.365M
→
1.37M (nearest 1% value)
Example #3: 22k
PTC
TLOW = 0
°
C, THIGH = 50
°
C
R
TH
= 22k at 25
°
C,
R
TH(LOW)
= 6.53k at 0
°
C
R
TH(HIGH)
= 61.4k at 50
°
C
R9 = 43.9k
→
44.2k (nearest 1% value)
R9A = 154k
Sizing the Thermistor Hold Capacitor
During the hold interval, C7 must hold the voltage across
the thermistor relatively constant to avoid false readings.
A reasonable amount of ripple on NTC during the hold
interval is about 10mV to 15mV. Therefore, the value of C7
is given by:
C7 = t
HOLD
/(R9/7 –ln(1 – 8 15mV/4.5V))
= 10 R
RT
17.5pF/(R9/7 –ln(1 – 8 15mV/4.5V)
Example:
R9 = 24.3k
R
RT
= 309k (~2 hour timer)
C7 = 0.51
μ
F
→
0.56
μ
F (nearest value)
W
U
U
Disabling the Thermistor Function
If the thermistor is not needed, connecting a resistor
between DCIN and NTC will disable it. The resistor should
be sized to provide at least 10
μ
A with the minimum voltage
applied to DCIN and 10V at NTC. Generally, a 301k resistor
will work for DCIN less than 15V. A 499k resistor is
recommended for DCIN greater than 15V.
Conditioning Depleted Batteries
Severely depleted batteries, with less than 2.5V/cell, should
be conditioned with a trickle charge to prevent possible
damage. This trickle charge is typically 10% of the 1C rate
of the battery. The LTC4007 can automatically trickle
charge depleted batteries using the circuit in Figure 11. If
the battery voltage is less than 2.5V/cell (2.44V/cell if
CHEM is low) then the LOBAT indicator will be low and Q4
is off. This programs the charging current with R
PROG
= R6
+ R14. Charging current is approximately 300mA. When
the cell voltage becomes greater than 2.5V the LOBAT
indicator goes high, Q4 shorts out R13, then R
PROG
= R6.
Charging current is then equal to 3A.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant prob-
lems, proper layout of the components connected to the IC
is essential. (See Figure 12.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that con-
nect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
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