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參數(shù)資料
| 型號： | LTC4221 |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Dual Hot Swap Controller/ Power Sequencer with Dual Speed, Dual Level Fault Protection |
| 中文描述： | 雙熱插拔控制器/電源與雙速序列，雙級故障保護(hù) |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 311K |
| 代理商： | LTC4221 |
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21
LTC4221
4221f
0.4V
V
TH
1.234V
1.9
μ
A
20
μ
A
<9.5
μ
A
9.5
μ
A
9.5
μ
A
DISCHARGE
BY LOAD
4221 F14
0.851V
0.4V
1.234V
1 2
V
CCn
V
ONn
V
TIMER
V
GATE2
V
OUT2
I
RSENSE2
3 4 5 6
7 8
9
A
REGULATED AT 25mV/R
SENSE
REGULATED AT
V
SENSE(ACL)
(t)/R
SENSE
RESET
STATE
INITIAL
TIMING
CHANNEL 2
START-UP
NORMAL
CYCLE
Start-Up Cycle With Current Limit
During a channel start-up cycle, if the inrush current as
according to Equation (12) is large enough to cause a
voltage drop greater than the active current limit threshold
(V
SENSE(ACL)
) across the sense resistor, an internal servo
loop controls the operation of the 9.5
μ
A current source at
the GATE pin to regulate the load current to:
V
R
SENSE
The active current limit threshold for channel nhas a
component controlled by the voltage at the FBnpin. When
FBn = 0V, V
SENSE(ACL)
= 9mV. As V
OUTn
and FBnramp up,
V
SENSE(ACL)
increases linearly until FBnreaches 0.5V,
where V
SENSE(ACL)
saturates at 25mV. In this fashion, the
inrush current is controlled by this “foldback” limiting that
tends to keep the power dissipation in the external MOSFET
constant during the start-up cycle.
The timing diagram in Figure 14 illustrates the operation of
the LTC4221 in a channel start-up cycle with limited inrush
I
INRUSH
SENSE ACL
=
(
)
(13)
current as described by Equation 13. Between time points
5 and 6, the GATE2 pin ramps up with I
GATE
= 9.5
μ
A. At
time point 6, the inrush current increases enough to trip
V
SENSE(ACL)
(t) and an internal servo loop engages, limiting
the inrush current to the level as in Equation 13 by
decreasing I
GATE
(<9.5
μ
A). As a result, the ramp rate of
both V
GATE2
and V
OUT2
decreases and V
SENSE2
increases
linearly until it saturates at 25mV at time point 7. At time
point 8, the external MOSFET enters triode operation.
I
INRUSH
drops as the ramp rate of V
OUT2
falls below that of
V
GATE2
so I
GATE
reverts back to 9.5
μ
A. At time point 9, the
internal servo loop to control I
INRUSH
is disengaged and
channel 2 slow comparator is armed, ending the channel 2
start-up cycle. So if C
LOAD2
is not fully charged up at this
point, I
INRUSH
will be subject to the slow comparator
threshold and actions as outlined in the Electronic Circuit
Breaker section. For a successful channel start-up, the
current limited part of the V
OUT
ramp-up (time points 6 and
8 of Figure 14) must not exceed the sum of start-up cycle
delay as given by Equation 10 and the slow comparator
response time as given by Equation 1. An example of an
unsuccessful start-up is Figure 11 which shows a channel
powering up into an overcurrrent at the load.
The fast comparators of both channels are armed at the
end of the initial timing cycle at time point 4 of Figure 14.
If a short circuit during the start-up cycle overrides the
servo loop and causes V
RSENSE
of either channel to exceed
100mV for more than 1
μ
s, the electronic circuit breaker
trips and the LTC4221 enters the fault state.
Frequency Compensation at Start-Up Cycle
If a channel’s external gate input capacitance (C
ISS
) is
greater than 600pF, no external gate capacitor is required
at GATE to stabilize the internal current-limiting loop dur-
ing start-up with current limit. The servo loop that controls
the external MOSFET during current limiting has a unity-
gain frequency of about 105kHz and phase margin of 80
°
for external MOSFET gate input capacitances to 2.5nF.
Power MOSFET
Power MOSFETs can be classified by R
DS(ON)
at V
GS
gate
drive ratings of 10V, 4.5V, 2.5V and 1.8V. Those rated for
R
DS(ON)
at 10V V
GS
usually have a higher V
GS
absolute
maximum rating than those at 4.5V and 2.5V. At low
APPLICATIOU
W
U
U
Figure 14. Channel 2 Start-Up with Current Limit
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