參數(shù)資料
型號(hào): LTC4221
廠商: Linear Technology Corporation
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual Hot Swap Controller/ Power Sequencer with Dual Speed, Dual Level Fault Protection
中文描述: 雙熱插拔控制器/電源與雙速序列,雙級故障保護(hù)
文件頁數(shù): 8/28頁
文件大?。?/td> 311K
代理商: LTC4221
8
LTC4221
4221f
PU
ON1
(Pin 1):
System/Channel 1 On Input. Both GATE pins
are pulled low by internal 100
μ
A pull-downs and the
FAULT latch is reset when V
ON1
< 0.4V. When 0.425V <
V
ON1
< 0.821V, the FAULT latch is released from reset.
When V
ON1
> 0.851V, GATE1 ramps up after an initial
timing cycle.
V
CC1
(Pin 2):
Channel 1 Positive Supply Input. It powers
all the internal circuitry. V
CC1
can range from 2.7V to 13.5V
for normal operation but it must be
V
CC2
. An undervolt-
age lockout circuit disables both channels whenever the
voltage at V
CC1
is less than 2.5V.
SENSE1
(Pin 3):
Channel 1 Current Sense Input. A sense
resistor R
SENSE1
is placed in the supply path between V
CC1
and SENSE1 to sense channel 1 load current. If V
RSENSE1
exceeds 100mV for more than 1
μ
s or 25mV for an adjust-
able time (set by the C
FILTER
), the FAULT latch is set and
fast pull-down circuits are triggered to discharge both
GATEs
low. During the start-up cycle, GATE1
ramp-up is
controlled to servo V
RSENSE1
V
SENSE(ACL)
. V
SENSE(ACL)
increases from 9mV to 25mV as V
FB1
ramps from 0V to
0.5V. To disable the current limit and circuit breaker
function for channel 1, tie SENSE1 to V
CC1
.
GATE1 (Pin 4):
Channel 1 Gate Drive. This pin is the high
side gate drive of an external N-channel MOSFET. When
V
ON1
< 0.821V, GATE1 is held low by a 100
μ
A current
source. When V
ON1
> 0.851V, an initial timing cycle is
followed by a start-up cycle when an internal charge pump
provides a 9.5
μ
A pull-up to ramp up GATE1 with inrush
current limiting. UVLO, overvoltage, overcurrent and ex-
ternally generated faults override the ON1 pin and pull
GATE1 low.
FB1
(Pin 5):
V
OUT1
Feedback Input. FB1
monitors the
channel 1 output voltage with an external resistive divider.
When V
FB1
< 0.617V, the PWRGD1
pin is pulled low. When
V
FB1
> 0.822V, overvoltage is detected, the FAULT latch is
set and both GATEs are pulled low. The FB1
pin is also used
to control the channel 1 current limit during its start-up
cycle.
PWRGD1 (Pin 6):
Channel 1 Power Good Output. PWRGD1
is pulled low when V
FB1
< 0.617V, during the initial timing
cycle or when the chip is in UVLO. An external pull-up is
required to generate a logic high at the open-drain PWRGD1
pin.
TYPICAL PERFOR U
V
PWRGD(OL)
/V
FAULT(OL)
vs Temperature
tp
(SC-FAULT)
vs Temperature
TEMPERATURE (
°
C)
–50
V
O
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0
0
50
75
4221 G37
–25
25
100
125
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
CC2
= 1V, I
PWRGD
/I
FAULT
= 1.6mA
TEMPERATURE (
°
C)
–50
t
(
16
17
18
25
75
4221 G38
15
14
–25
0
50
100
125
13
12
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
= 1V
TIMER = 0.5V
TEMPERATURE (
°
C)
–50
t
(
1.4
1.6
1.8
25
75
4221 G39
1.2
1.0
–25
0
50
100
125
0.8
0.6
V
CC1
= 2.7V
V
CC1
= 5V
V
CC1
= 13.5V
V
= 1V
TIMER = 0.5V
tp
(FC-GATE)
vs Temperature
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