參數(shù)資料
型號: LTC4221IGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: Dual Hot Swap Controller/ Power Sequencer with Dual Speed, Dual Level Fault Protection
中文描述: 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁數(shù): 19/28頁
文件大?。?/td> 311K
代理商: LTC4221IGN
19
LTC4221
4221f
latch is cleared and the FAULT pin sources a 3.8
μ
A pull-up
current to charge up C
ON1
. The typical delay t
ON
is :
C
ON
=
(
)
3 8
t
V
V
A
ON
μ
0 851
.
1
–0 4
.
(3)
As shown in the timing diagram of Figure 11, the autoretry
circuitry will attempt to restart the LTC4221 with a duty
cycle:
t
STARTUP
+
(
+
t
t
ON
INITIAL
Duty Cycle =
)
+
+
t
t
t
FILTER
STARTUP
FILTER
%
100
(4)
t
FILTER
is defined in Equation 1 and t
ON
is defined in Equa-
tion 3. t
INITIAL
, the initial timing cycle delay, is given in
Equation 9 located in the Initial Timing Cycle section.
t
STARTUP
, the start-up cycle delay, is given in Equation 10
and found in the Start-Up Cycle Without Current Limit
section. Using the capacitor values as shown in Figure 10,
the Autoretry Duty cycle works out to be approximately 6%.
Sense Resistor Consideration
The fault current level at which the LTC4221’s internal
electronic circuit breaker trips is determined by sense
resistors connected between each channel’s V
CC
and
SENSE pins. For both channels, the slow comparator trip
current and the fast comparator trip current are given by
equations (5) and (6) respectively.
V
R
SENSE
V
R
R
SENSE
I
mV
R
TRIP SC
SENSE SC
SENSE
(
)
(
)
=
=
25
(5)
I
mV
TRIP FC
SENSE FC
SENSE
(
)
(
)
=
=
100
(6)
The power rating of the sense resistor should be rated at
the fault current level. Table 1 in the Appendix lists some
common sense resistors.
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and each channel’s
V
CC
and SENSE pins are strongly recommended. The
drawing in Figure 12 illustrates the connections between
the LTC4221 and the sense resistor. PCB layout should be
balanced and symmetrical to minimize wiring errors. In
addition, the PCB layout for the sense resistor should
include good thermal management techniques for optimal
sense resistor power dissipation.
Calculating Current Limit
For a selected R
SENSE
, the load current must not exceed
I
TRIP(SC)
. The minimum I
TRIP(SC)
is given by Equation 7:
V
R
SENSE MAX
(
where
I
mV
R
TRIP SCMIN
(
SENSE SCMIN
(
SENSE MAX
)
)
)
(
)
.
=
=
20 5
(7)
R
R
R
100
SENSE MAX
SENSE
TOL
(
)
=
+
1
The maximum I
TRIP(SC)
is given by Equation 8:
V
R
SENSE MIN
where
I
mV
R
TRIP SCMAX
(
SENSE SCMAX
(
SENSE MIN
)
)
(
)
(
)
.
=
=
29 5
(8)
R
R
R
100
SENSE MIN
SENSE
TOL
(
)
=
1
If a 7m
sense resistor with
±
1% tolerance is used for
current limiting, the nominal slow comparator trip current
is 3.57A. From Equations 7 and 8, I
TRIP(SCMIN)
= 2.9A and
I
TRIP(SCMAX)
= 4.26A. For proper operation, the minimum
I
TRIP(SC)
must exceed the circuit maximum operating load
current. For reliability purposes, the operation at the
maximum trip current must be evaluated carefully. If
necessary, two resistors with the same R
TOL
can be
connected in parallel to yield a nominal R
SENSE
value that
fits the circuit requirements.
APPLICATIOU
W
U
U
SENSE RESISTOR
TO
V
CCn
TO
SENSEn
CURRENT FLOW
TO LOAD
CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMP
ON 1oz COPPER
W
4221 F12
Figure 12. PCB Connections to the Sense Resistor
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