values of CDET, RDET " />
參數(shù)資料
型號(hào): LTC4259ACGW#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 15/32頁(yè)
文件大?。?/td> 0K
描述: IC CTRLR POE QUAD AC DISC 36SSOP
標(biāo)準(zhǔn)包裝: 1,000
控制器類(lèi)型: 以太網(wǎng)供電控制器(POE)
接口: I²C
電源電壓: 3 V ~ 4 V
電流 - 電源: 2.5mA
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 36-SSOP
包裝: 帶卷 (TR)
LTC4259A
22
4259afb
values of CDET, RDET and CPSE is discouraged. Contact the
LTC Applications department for additional support.
When choosing CDET and CPSE, carefully consider voltage
derating of the capacitors. Capacitors built around an X7R
dielectric will have about 60% of the specified capacitance
at their rated voltage. Operated at half their rated voltage,
X7R capacitors exhibit more than 80% of their specified
capacitance. With other ceramic dielectrics commonly
used in 50V and 100V chip capacitors, capacitance falls
much more dramatically with voltage. At their rated volt-
age, Y5V or Z5U capacitors exhibit less than 30% of their
zero-bias capacitance. Ceramic capacitors can also have
significantly less capacitance at elevated temperatures. In
order to produce the desired capacitance at the operating
bias, 100V or 250V X7R capacitors should be used with
the LTC4259A.
As illustrated in Figure 19, the Power over Ethernet con-
nection between the PSE and PD includes a large amount
of capacitance. Cable capacitance is particularly troubling
because CAT-3 and CAT-5 pair-to-pair capacitance is not
tightly specified by the IEEE 802.3 standard or well con-
trolled by cable manufacturers. Considering that patch
panels, additional connectors, old wiring, etc. are likely to
be placed between the PSE and PD, pair-to-pair capaci-
tance is a pretty nebulous quantity. Consequently, the
cable’s contribution to the port impedance (at the fre-
quency used for AC disconnect) can be a concern.
Assumimg that fOSCIN is 100Hz, the 0.1F of CPSE plus
0.05
F of cable capacitance gives a port impedance of 10k
at 100Hz. The PD AC signature resistance is about 25k.
Connecting a PD with the maximum allowed resistance of
26.25k brings the connection impedance to about 8k. The
presence of a PD only makes a 20% reduction in the port
impedance requiring the AC disconnect circuitry to be
quite sensitive. When the OSCIN pin is driven with a sine
wave, the LTC4259A is able to distinguish between capaci-
tive impedance and resistive impedance on the Power over
Ethernet connection. AC disconnect is reliable for cable
capacitance up to about 0.2
F, nearly an order of magni-
tude greater than worst case for a long CAT-3 or CAT-5
cable.
APPLICATIO S I FOR ATIO
WU
UU
Figure 18. AC Disconnect Single Port Application Circuit (Port 4 Shown)
Figure 19. Simplified AC Disconnect Circuit with Impedances at 100Hz
LEVEL
SHIFT
DETECT4
AGND
DGND
OSCIN
1/4
LTC4259A
–48V
GND
OUT4
ROUT4
10k
RS4
0.5
1%
DDET4
CMPD3003
PD
RDET4
1k
RPD_D
≤26.25k
CPD_D
≥0.05F
CDET4
0.47
F
100V X7R
CPSE4
0.1
F
100V X7R
4259A F18
DAC4
S1B
Q4
GATE4
SENSE4
VEE
OSCILLATOR
INPUT
CURRENT
SENSE
RDET
1k
ZLINK < 14k
ZCABLE < 32k
PD
~16k
~7k
ZPD < 14k
CDET
0.47
F
CPSE
0.10
F
CCABLE ≤ 0.05F
<32k
CPD_D ≥ 0.05FRPD_D < 26.25k
4259A F19
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