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參數(shù)資料
| 型號(hào)： | LTC4269CDKD-2 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 560 kHz SWITCHING FREQ-MAX, PDSO32 |
| 封裝： | 7 X 4 MM, PLASTIC, M0-229, DFN-32 |
| 文件頁數(shù)： | 19/34頁 |
| 文件大小： | 383K |
| 代理商： | LTC4269CDKD-2 |
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LTC4269-2
42692fb
(3) The maximum duty cycle clamp calculated in (2)
should be programmed to be 10% greater than the
maximum operational duty cycle calculated in (1).
Simple adjustment of maximum duty cycle can be
achieved by adjusting SS_MAXDC.
Example calculation for (2):
For RT = 35.7k, RB = 100k, VREF = 2.5V,
RDELAY = 40k, fOSC = 200kHz and SD_VSEC = 1.32V,
this gives SS_MAXDC(DC) = 1.84V, tDELAY = 40ns
and k = 1
Maximum Duty Cycle Clamp
= 1 0.522(1.84/1.32) – (40ns 200kHz)
= 0.728 – 0.008 = 0.72 (Duty Cycle Clamp = 72%)
Note 1: To achieve the same maximum duty cycle clamp at
100kHz as calculated for 200kHz, the SS_MAXDC voltage
should be reprogrammed by,
SS_MAXDC(DC) (100kHz)
= SS_MAXDC(DC) (200kHz) k (200kHz)/k (100kHz)
= 1.84 1.0/1.055 = 1.74V (k = 1.055 for 100kHz)
Note 2 : To achieve the same maximum duty cycle clamp
while synchronizing to an external clock at the SYNC pin,
the SS_MAXDC voltage should be reprogrammed as,
SS_MAXDC (DC) (fsync)
= SS_MAXDC (DC) (200kHz) [(fosc/fsync) +
0.09(fosc/200kHz)0.6]
For SS_MAXDC (DC) (200kHz) = 1.84V for 72%
duty cycle
SS_MAXDC (DC) (fsync = 250kHz) for 72%
duty cycle
= 1.84 [(200kHz/250kHz) + 0.09(1)0.6]
= 1.638V
Programming Soft-Start Timing
The LTC4269-2 has built-in soft-start capability to provide
low stress controlled start-up from a list of fault condi-
tions that can occur in the application (see Figures 16
and 17). The LTC4269-2 provides true PWM soft-start by
applicaTions inForMaTion
creates the volt-second clamp. The maximum duty cycle
clamp can be adjusted by programming voltage on the
SS_MAXDC pin using a resistor divider from VREF. An
increase of voltage at the SS_MAXDC pin causes the
maximum duty cycle clamp to increase.
To program the volt-second clamp, the following steps
should be taken:
(1) The maximum operational duty cycle of the converter
should be calculated for the given application.
(2) An initial value for the maximum duty cycle clamp
should be calculated using the equation below with a
first pass guess for SS_MAXDC.
Note: Since maximum operational duty cycle occurs at
minimum system input voltage (UVLO), the voltage at the
SD_VSEC pin = 1.32V.
Max Duty Cycle Clamp (OUT Pin) =
k 0.522(SS_MAXDC(DC)/SD_VSEC) – (tDELAY fOSC)
where:
SS_MAXDC(DC) = VREF(RB/(RT + RB)
SD_VSEC = 1.32V at minimum system input voltage
tDELAY = programmed delay between SOUT and OUT
k = 1.11 – 5.5e–7 (fOSC)
POWER SUPPLY
INPUT VOLTAGE
ADAPTIVE
DUTY CYCLE
CLAMP INPUT
MAX DUTY CYCLE
CLAMP ADJUST INPUT
*MINIMUM ALLOWABLE RT IS 10k TO
GUARANTEE SOFT-START PULL-OFF
42692 F15
SD_VSEC
SS_MAXDC
VREF
LTC4269-2
R1
R2
RB
RT*
Figure 15. Programming Maximum Duty Cycle Clamp
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