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參數(shù)資料
| 型號： | LTC6601IUF-2#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 37/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRVR FILTER/ADC LN 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 頻率 - 截止或中心： | 27MHz |
| 濾波器數(shù)： | 3 |
| 濾波器階數(shù)： | 2nd |
| 電源電壓： | 2.7 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤（4x4） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1323 (CN2011-ZH PDF) |
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LTC6601-2
6
66012f
Note 1: Stresses beyond those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. Exposure to any
Absolute Maximum Rating condition for extended periods may affect
device reliability and lifetime.
Note 2: All pins are protected by steering diodes to either supply. If any
pin is driven beyond the part’s supply voltage, the excess input current
(current in excess of what it takes to drive that pin to the supply rail)
should be limited to less than 10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the Absolute Maximum Rating when the output is shorted
indenitely. Long-term application of output currents in excess of the
Absolute Maximum Ratings may impair the life of the device.
Note 4: The LTC6601C/LTC6601I are guaranteed functional over the
operating temperature range –40°C to 85°C.
Note 5: The LTC6601C is guaranteed to meet specied performance from
0°C to 70°C. The LTC6601C is designed, characterized, and expected
to meet specied performance from –40°C to 85°C but is not tested or
QA sampled at these temperatures. The LTC6601I is guaranteed to meet
specied performance from –40°C to 85°C.
Note 6: Output referred voltage offset is a function of the low frequency
gain of the LTC6601. To determine output referred voltage offset, or output
voltage offset drift, multiply this specication by the noise gain (1 + GAIN).
See Applications Information for more details.
Note 7: Input bias current is dened as the average of the currents
owing into the noninverting and inverting inputs of the internal amplier
and is calculated from measurements made at the pins of the IC. Input
offset current is dened as the difference of the currents owing into the
noninverting and inverting inputs of the internal amplier and is calculated
from measurements made at the pins of the IC.
Note 8: Input common mode range is tested using the test circuit of
Figure 1 by measuring the differential DC gain with VICM = mid-supply, and
with VICM at the input common mode range limits listed in the Electrical
Characteristics table, verifying the differential gain has not deviated from
the mid-supply common mode input case by more than 1%, and the
common mode offset (VOCMOS) has not deviated from the mid-supply
common mode offset by more than ±20mV.
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by measuring the differential DC gain with VOCM =
mid-supply, and again with a voltage set on the VOCM pin at the Electrical
Characteristics table limits, checking the differential gain has not deviated
from the mid-supply common mode input case by more than 1%, and that
the common mode offset (VOCMOS) has not deviated by more than ±20mV
from the mid-supply case.
Note 9: Input CMRR is dened as the ratio of the change in the input
common mode voltage at the amplier input to the change in differential
input referred voltage offset. Output CMRR is dened as the ratio of the
change in the voltage at the VOCM pin to the change in differential input
referred voltage offset.
Note 10: Power supply rejection (PSRR) is dened as the ratio of the
change in supply voltage to the change in differential input referred voltage
offset. Common mode power supply rejection (PSRRCM) is dened as the
ratio of the change in supply voltage to the change in the common mode
offset, VOUTCM/VOCM.
Note 11: Output swings are measured as differences between the output
and the respective power supply rail.
Note 12: Extended operation with the output shorted may cause junction
temperatures to exceed the 150°C limit and is not recommended.
Note 13: Floating the BIAS pin will reliably place the part into the half-
power mode. The pin does not have to be driven. Care should be taken,
however, to prevent external leakage currents in or out of this pin from
pulling the pin into an undesired state.
Note 14: The variable contact resistance of the high speed test equipment
limits the accuracy of this test. These parameters only show a typical
value, or conservative minimum and maximum value.
ELECTRICAL CHARACTERISTICS
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| LTC6601IUF-2TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Low Power, Low Distortion, 5MHz to 27MHz, Pin Confi gurable Filter/ADC Driver |
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| LTC6602CUF#PBF | 功能描述:IC FILTER BANDPASS/LOWPASS 24QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 濾波器 - 有源 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 濾波器類型:連續(xù)時間，帶通低通 頻率 - 截止或中心:150kHz 濾波器數(shù):4 濾波器階數(shù):8th 電源電壓:4.74 V ~ 11 V，±2.37 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) |
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