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參數(shù)資料
| 型號： | LTC690 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Microprocessor Supervisory Circuits(μP監(jiān)控電路) |
| 中文描述： | 微處理器監(jiān)控電路（微處理器監(jiān)控電路） |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 145K |
| 代理商： | LTC690 |
11
LTC 690/LTC 691
LTC 694/LTC 695
Power-Fail Warning
The LTC690 family generates a Power Failure Output
(PFO) for early warning of failure in the microprocessor's
power supply. This is accomplished by comparing the
Power Failure Input (PFI) with an internal 1.3V reference.
PFO goes low when the voltage at the PFI pin is less than
1.3V. Typically PFI is driven by an external voltage divider
(R1 and R2 in Figures 8 and 9) which senses either an
unregulated DC input or a regulated 5V output. The voltage
divider ratio can be chosen such that the voltage at the PFI
pin falls below 1.3V several milliseconds before the 5V
supply falls below the maximum reset voltage threshold
4.75V. PFO is normally used to interrupt the microproces-
sor to execute shutdown procedure between PFO and
RESET or RESET.
The power-fail comparator, C3, does not have hysteresis.
Hysteresis can be added however, by connecting a resis-
tor between the PFO output and the noninverting PFI input
pin as shown in Figures 8 and 9. The upper and lower trip
points in the comparator are established as follows:
When PFO output is low, R3 sinks current from the
summing junction at the PFI pin.
When PFO output is high, the series combination of R3 and
R4 source current into the PFI summing junction.
Example 1:
The circuit in Figure 8 demonstrates the use of
the power-fail comparator to monitor the unregulated
power supply input. Assuming the the rate of decay of the
supply input V
IN
is 100mV/ms and the total time to execute
a shutdown procedure is 8ms. Also the noise of V
IN
is
200mV. With these assumptions in mind, we can reason-
ably set V
L
= 7.5V which 1.25V greater than the sum of
maximum reset voltage threshold and the dropout voltage
U
S
A
O
PPLICATI
U
U
V =1.3V 1+R1
R2
R1
R3
+
V
1.3V 1
R2±(5V±1.3V)R1
1.3V(R3 R4)
L
=
+
Assuming R4
R3,V
5VR1
R3
HYSTERESIS
<<
=
5V
0.1
μ
F
3V
10
μ
F
V
BATT
V
CC
LTC691
LTC695
V
OUT
GND
690 F06
V
CC
62512
RAM
RESET
CE IN
RESET
CE OUT
0.1
μ
F
TO
μ
P
FROM DECODER
CS
20ns PROPAGATION DELAY
GND
+
Figure 6. A Typical Nonvolatile CMOS RAM Application
Figure 9. Monitoring RegulatedDC Supply
with the LTC690's Power-Fail Comparator
10
μ
F
10
μ
F
V
IN
V
OUT
ADJ
1690 F09
0.1
μ
F
TO
μ
P
LT1086-5
V
IN
≥
6.5V
+
R4
10k
R3
2.7M
R1
27k
R2
8.2k
5V
R5
3.3k
V
CC
GND
PFO
PFI
LTC690/LTC691
LTC694/LTC695
+
10
μ
F
100
μ
F
R3
300k
V
IN
V
OUT
ADJ
690 F08
V
CC
0.1
μ
F
R4
10k
TO
μ
P
PFO
PFI
GND
LT1086-5
V
IN
≥
7.5V
LTC690/LTC691
LTC694/LTC695
R1
51k
R2
10k
5V
+
+
Figure 8. Monitoring UnregulatedDC Supply
with the LTC690's Power-Fail Comparator
5V
3V
0.1
μ
F
10
μ
F
V
BATT
V
CC
LTC690
LTC694
V
OUT
GND
690 F07
V
CC
RESET
0.1
μ
F
CS
62128
RAM
CS1
CS2
GND
+
Figure 7. Write Protect for RAM with LTC690 or LTC694
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC690_1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Microprocessor Supervisory Circuits |
| LTC6900 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Low Power, 1kHz to 20MHz Resistor Set SOT-23 Oscillator |
| LTC6900CS5 | 制造商:Linear Technology 功能描述:LOW POWER, 1KHZ TO 20MHZ RESISTOR SET SOT-23 OSCILLATOR |
| LTC6900CS5#PBF | 制造商:Linear Technology 功能描述:IC, PRECISION OSC, 20MHZ, 5.5V, TSOT235; Operating Mode:-; Frequency:20MHz; Supply Voltage Min:2.7V; Supply Voltage Max:5.5V; Digital IC Case Style:TSOT-23; No. of Pins:5; Clock External Input:No; Operating Temperature Min:-40C ;RoHS Compliant: Yes |
| LTC6900CS5#TR | 功能描述:IC OSC SILICON 20MHZ TSOT23-5 RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 可編程計時器和振蕩器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:45 系列:- 類型:溫度 - 補償晶體振蕩器（TCXO） 計數(shù):- 頻率:25MHz 電源電壓:3.135 V ~ 3.465 V 電流 - 電源:1.5mA 工作溫度:-40°C ~ 85°C 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 包裝:管件 供應商設備封裝:16-SOIC W 安裝類型:表面貼裝 |
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