參數(shù)資料
型號: LTC690
廠商: Linear Technology Corporation
英文描述: Microprocessor Supervisory Circuits(μP監(jiān)控電路)
中文描述: 微處理器監(jiān)控電路(微處理器監(jiān)控電路)
文件頁數(shù): 5/16頁
文件大小: 145K
代理商: LTC690
5
LTC 690/LTC 691
LTC 694/LTC 695
V
CC
:
5V Supply Input. The V
CC
pin should be bypassed
with a 0.1
μ
F capacitor.
V
OUT
:
Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1
μ
F or greater. During normal operation,
V
OUT
obtains power from V
CC
through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
on resistance of 5
. When V
CC
is lower than V
BATT
, V
OUT
is internally switched to V
BATT
. If V
OUT
and V
BATT
are not
used, connect V
OUT
to V
CC
.
V
BATT
:
Back-Up Battery Input. When V
CC
falls below V
BATT
,
auxiliary power, connected to V
BATT
, is delivered to V
OUT
through PMOS switch, M2. If back-up battery or auxiliary
power is not used, V
BATT
should be connected to GND.
W
I
DAGRA
BLOCK
GND:
Ground pin.
BATT ON:
Battery On Logic Output from Comparator C2.
BATT ON goes low when V
OUT
is internally connected to
V
CC
. The output typically sinks 35mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of V
OUT
. BATT ON goes
high when V
OUT
is internally switched to V
BATT
.
PFI:
Power Failure Input. PFI is the noninverting input to
the power-fail comparator, C3. The inverting input is
internally connected to a 1.3V reference. The power failure
output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or V
OUT
when
C3 is not used.
PI FU CTIO S
CHARGE
PUMP
M2
M1
VBATT
VCC
CE IN
PFI
OSC IN
OSC SEL
WDI
RESET PULSE
GENERATOR
WATCHDOG
TIMER
RESET
BATT ON
VOUT
C1
1.3V
GND
+
+
C2
OSC
TRANSITION
DETECTOR
+
C3
WDO
RESET
PFO
LOW LINE
CE OUT
690 BD
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