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參數(shù)資料
| 型號： | LTC6945IUFD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER INTEGER N 28QFN |
| 軟件下載： | PLLWizard™ PLLWizard™, with .NET 2.0 installer |
| 標準包裝： | 73 |
| 類型： | * |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.15 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 28-QFN（4x5） |
| 包裝： | 管件 |
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LTC6945
10
6945f
OPERATION
Figure 1. Simplified REF Interface Schematic
Figure 2. Simplified REFO Interface Schematic
The LTC6945 is a high performance PLL, and, combined
with an external high performance VCO, can produce low
noise LO signals up to 6GHz. It is able to achieve superior
integrated phase noise performance due to its extremely
low in-band phase noise performance.
REFERENCE INPUT BUFFER
The PLL’s reference frequency is applied differentially on
pins REF+ and REF–. These high impedance inputs are
self-biased and must be AC-coupled with 470pF capacitors
(see Figure 1 for a simplified schematic). Alternatively, the
inputs may be used single-ended by applying the refer-
ence frequency at REF+ and bypassing REF– to GND with
a 470pF capacitor.
Table 1. FILT[1:0] Programming
FILT[1:0]
fREF
3
<20MHz
2NA
1
20MHz to 50MHz
0
>50MHz
Table 2. BST Programming
BST
VREF
1
<2.0VP-P
0
≥2.0VP-P
REFERENCE OUTPUT BUFFER
The reference output buffer produces a low noise square
wave with a noise floor of –155dBc/Hz (typical) at 10MHz.
Its output is low impedance, and produces 2dBm typical
output power into a 50Ω load at 10MHz. Larger output
swings will result if driving larger impedances. The out-
put is self-biased, and must be AC-coupled with a 22nF
capacitor (see Figure 2 for a simplified schematic). The
buffer may be powered down by using bit PDREFO found
in the serial port Power register h02.
27
28
4.2k
REF+
REF–
BST
FILT[1:0]
LOWPASS
4.2k
6945 F01
1.9V
BIAS
VREF
+ VREF+
A high quality signal must be applied to the REF± inputs
as they provide the frequency reference to the entire PLL.
To achieve the part’s in-band phase noise performance,
apply a CW signal of at least 6dBm into 50Ω, or a square
wave of at least 0.5VP-P with slew rate of at least 40V/μs.
Additional options are available through serial port register
h08 to further refine the application. Bits FILT[1:0] control
the reference input buffer’s lowpass filter, and should be
set based upon fREF to limit the reference’s wideband
noise. The FILT[1:0] bits must be set correctly to reach
the LM(NORM) normalized in-band phase noise floor. See
Table 1 for recommended settings.
The BST bit should be set based upon the input signal level
to prevent the reference input buffer from saturating. See
Table 2 for recommended settings and the Applications
Information section for programming examples.
2
REFO
VREFO
+
800Ω
6945 F02
REFERENCE (R) DIVIDER
A 10-bit divider, R_DIV, is used to reduce the frequency
seen at the PFD. Its divide ratio R may be set to any
integer from 1 to 1023, inclusive. Use the RD[9:0] bits
found in registers h03 and h04 to directly program the R
divide ratio. See the Applications Information section for
the relationship between R and the fREF, fPFD, fVCO and
fRF frequencies.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6946-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-2 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946-3 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC6946IUFD-1#PBF | 功能描述:IC INTEGER-N PLL W/VCO 28-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| LTC6946IUFD-1#TRPBF | 功能描述:IC INTEGER-N PLL W/VCO 28QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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