參數(shù)資料
型號(hào)： LTC6992CDCB-4#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 10/34頁(yè)
文件大?。?/td> 0K
描述： IC OSC SILICON 1MHZ 6-DFN
產(chǎn)品培訓(xùn)模塊： TimerBlox Family Timing Devices
產(chǎn)品目錄繪圖： LTC699_DFN
特色產(chǎn)品： TimerBlox?
標(biāo)準(zhǔn)包裝： 2,500
系列： TimerBlox®
類型： 振蕩器 - 硅
頻率： 3.81Hz ~ 1MHz
電源電壓： 2.25 V ~ 5.5 V
電流 - 電源： 365µA
工作溫度： 0°C ~ 70°C
封裝/外殼： 6-WFDFN 裸露焊盤
包裝： 帶卷 (TR)
供應(yīng)商設(shè)備封裝： 6-DFN-EP（2x3）
安裝類型： 表面貼裝
配用： DC1562A-C-ND - BOARD EVAL LTC6992-1
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
18
69921234fc
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring VDIV for changes. Changes to DIVCODE will
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
tDIVCODE = 16 (DIVCODE + 6) tMASTER
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
AdigitalfilterisusedtoguaranteetheDIVCODEhassettled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
operaTion
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, tSTART. The OUT pin
is held low during this time. The typical value for tSTART
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of NDIV):
tSTART(TYP) = 500 tMASTER
The output will begin oscillating after tSTART. If POL = 0
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
never be less than 25% of tOUT.
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin volt-
ages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
track V+. Less than 100pF will not affect performance.
6992 F06
OUT
DIV
STABLE VDIV
V+
tDIVCODE
tSTART
1ST PULSE WIDTH MAY BE INACCURATE
Figure 5. DIVCODE Change from 3 to 1
Figure 6. Start-Up Timing Diagram
DIV
0.5V/DIV
OUT
1V/DIV
V+ = 3.3V
RSET = 200k
VMOD = 0.3V
100s/DIV
6992 F05
512s
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC6992CDCB6-1-PBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)
LTC6992CDCB6-1-TRPBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)
LTC6992CDCB6-2-PBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)
LTC6992CDCB6-2-TRPBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)
LTC6992CDCB6-3-PBF 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM)
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