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參數(shù)資料
| 型號： | LTC6992CDCB-4#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OSC SILICON 1MHZ 6-DFN |
| 產品培訓模塊： | TimerBlox Family Timing Devices |
| 產品目錄繪圖： | LTC699_DFN |
| 特色產品： | TimerBlox? |
| 標準包裝： | 2,500 |
| 系列： | TimerBlox® |
| 類型： | 振蕩器 - 硅 |
| 頻率： | 3.81Hz ~ 1MHz |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 電流 - 電源： | 365µA |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 供應商設備封裝： | 6-DFN-EP（2x3） |
| 安裝類型： | 表面貼裝 |
| 配用： | DC1562A-C-ND - BOARD EVAL LTC6992-1 |
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LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
15
69921234fc
Table 1 offers recommended 1% resistor values that ac-
curately produce the correct voltage division as well as the
corresponding NDIVandPOLvaluesfortherecommended
resistor pairs. Other values may be used as long as:
1. The VDIV/V+ ratio is accurate to ±1.5% (including resis-
tor tolerances and temperature effects).
2. Thedrivingimpedance(R1||R2)doesnotexceed500kΩ.
If the voltage is generated by other means (i.e. the output
of a DAC) it must track the V+ supply voltage. The last
column in Table 1 shows the ideal ratio of VDIV to the
supply voltage, which can also be calculated as:
VDIV
V+
=
DIVCODE
+ 0.5
16
±1.5%
Forexample,ifthesupplyis3.3VandthedesiredDIVCODE
is 4, VDIV = 0.281 3.3V = 928mV ± 50mV.
Figure 2 illustrates the information in Table 1, showing
that NDIV is symmetric around the DIVCODE midpoint.
Table 1. DIVCODE Programming
DIVCODE
POL
NDIV
RECOMMENDED fOUT
R1 (kΩ)
R2 (kΩ)
VDIV/V+
0
1
62.5kHz to 1MHz
Open
Short
≤0.03125 ±0.015
1
0
4
15.63kHz to 250kHz
976
102
0.09375 ±0.015
2
0
16
3.906kHz to 62.5kHz
976
182
0.15625 ±0.015
3
0
64
976.6Hz to 15.63kHz
1000
280
0.21875 ±0.015
4
0
256
244.1Hz to 3.906kHz
1000
392
0.28125 ±0.015
5
0
1024
61.04Hz to 976.6Hz
1000
523
0.34375 ±0.015
6
0
4096
15.26Hz to 244.1Hz
1000
681
0.40625 ±0.015
7
0
16384
3.815Hz to 61.04Hz
1000
887
0.46875 ±0.015
8
1
16384
3.815Hz to 61.04Hz
887
1000
0.53125 ±0.015
9
1
4096
15.26Hz to 244.1Hz
681
1000
0.59375 ±0.015
10
1
1024
61.04Hz to 976.6Hz
523
1000
0.65625 ±0.015
11
1
256
244.1Hz to 3.906kHz
392
1000
0.71875 ±0.015
12
1
64
976.6Hz to 15.63kHz
280
1000
0.78125 ±0.015
13
1
16
3.906kHz to 62.5kHz
182
976
0.84375 ±0.015
14
1
4
15.63kHz to 250kHz
102
976
0.90625 ±0.015
15
1
62.5kHz to 1MHz
Short
Open
≥0.96875 ±0.015
operaTion
Figure 2. Frequency Range and POL Bit vs DIVCODE
0.5V+
f OUT
(kHz)
6992 F02
1000
100
10
1
0.001
0.1
0.01
INCREASING VDIV
V+
0V
POL BIT = 0
POL BIT = 1
0
15
1
3
2
5
4
7
6
9
8
11
10
13
12
14
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC6992CDCB6-1-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM) |
| LTC6992CDCB6-1-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM) |
| LTC6992CDCB6-2-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM) |
| LTC6992CDCB6-2-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM) |
| LTC6992CDCB6-3-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox Voltage-Controlled Pulse Width Modulator (PWM) |
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