參數(shù)資料
型號(hào)： LTC6992IDCB-4#TRMPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 0.02 A SWITCHING CONTROLLER, PDSO6
封裝： 2 X 3 MM, LEAD FREE, PLASTIC, MO-229, DFN-6
文件頁(yè)數(shù)： 13/34頁(yè)
文件大?。?/td> 2577K
代理商： LTC6992IDCB-4#TRMPBF
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
20
69921234fb
APPLICATIONS INFORMATION
ing a large RSET resistor. POL = 0 and NDIV = 4 requires
DIVCODE = 1. Using Table 1, choose the R1 and R2 values
to program DIVCODE = 1.
Step 4: Select RSET
Calculate the correct value for RSET using Equation (1b).
RSET =
1MHz 50k
4 20kHz
= 625k
Since 625k is not available as a standard 1% resistor,
substitute 619k if a 0.97% frequency shift is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 7.
6992 F07
LTC6992-4
MOD
GND
SET
OUT
V+
DIV
R1
976k
DIVCODE = 1
R2
102k
RSET
625k
VMOD
2.25V TO 5.5V
Figure 7. 20kHz PWM Oscillator
Figure 8. Duty Cycle Variation Due to ΔVSET
VMOD (V)
0
DUT
Y
CYCLE
(%)
100
90
70
80
60
50
30
40
20
10
0
0.6
0.2
6992 F08
1
0.4
0.8
ΔVSET = 0mV
ΔVSET = 30mV
ΔVSET = –30mV
Figure 9. Fixed-Frequency, Arbitrary Duty Cycle Oscillator
6992 F09
LTC6992-X
MOD
GND
SET
OUT
V+
DIV
R1
R2
RSET2
RSET1
2.25V TO 5.5V
D
5
4
R
SET 2
R
SET1
R
SET 2
1
8
Figure 8 demonstrates the worst-case impact of this varia-
tion (if VSET is at its 0.97V or 1.03V limits).
This error is in addition to the inherent PWM duty cycle
accuracy spec
D (±4.5%), so care should be taken if
accuracy at high duty cycles (VMOD near 0.9V) is critical.
Sensitivity to
VSET can be eliminated by making VMOD
proportional to VSET. For example, Figure 9 shows a simple
circuit for generating an arbitrary duty cycle. The equation
for duty cycle does not depend on VSET at all.
Duty Cycle Sensitivity to ΔVSET
The output duty cycle is proportional to the ratio of VMOD/
VSET. Since VSET can vary up to ±30mV from 1V it can
effectively gain or attenuate VMOD, as shown below when
VSET is added to the equation.
D
=
VMOD
0.8 VSET +ΔVSET
(
)
1
8
For many designs, the absolute VMODtodutycycleaccuracy
is not critical. For others, making the simplifying assump-
tion of
VSET = 0V creates the potential for additional
duty cycle error, which increases with VMOD, reaching a
maximum of 3.4% if
VSET = –30mV.
ΔD
VMOD
800mV
Δ
VSET
Dideal +
1
8
ΔV
SET
VSET
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