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參數(shù)資料
| 型號(hào)： | LTC6993HDCB-1#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MONOSTABLE MULTIVIBRATOR 6DFN |
| 產(chǎn)品培訓(xùn)模塊： | TimerBlox Family Timing Devices |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 系列： | LTC®6993 |
| 邏輯類型： | 單穩(wěn)態(tài) |
| 獨(dú)立電路： | 1 |
| 施密特觸發(fā)器輸入： | 無 |
| 傳輸延遲： | 11ns |
| 輸出電流高，低： | 16mA，16mA |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x3） |
| 包裝： | 帶卷 (TR) |
| 配用： | DC1562A-D-ND - BOARD EVAL LTC6992-2 |
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LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
18
69931234fb
ISET Extremes (Master Oscillator Frequency Extremes)
When operating with ISET outside of the recommended
1.25A to 20A range, the master oscillator operates
outside of the 62.5kHz to 1MHz range in which it is most
accurate.
The oscillator will still function with reduced accuracy for
ISET < 1.25A. At approximately 500nA, the oscillator will
stop. Under this condition, the output pulse can still be
initiated, but will not terminate until ISET increases and
the master oscillator starts again.
At the other extreme, it is not recommended to operate
the master oscillator beyond 2MHz because the accuracy
of the DIV pin ADC will suffer.
Settling Time
Following a 2
× or 0.5× step change in ISET, the output
pulse width takes approximately six master clock cycles
(6 tMASTER) to settle to within 1% of the final value. An
exampleisshowninFigure10,usingthecircuitinFigure 8.
Coupling Error
The current sourced by the SET pin is used to bias the
internal master oscillator. The LTC6993 responds to
changesinISETalmostimmediately,whichprovidesexcel-
lent settling time. However, this fast response also makes
the SET pin sensitive to coupling from digital signals, such
as the TRIG input.
Even an excellent layout will allow some coupling between
TRIG and SET. Additional error is included in the speci-
fied accuracy for NDIV = 1 to account for this. Figure 11
shows that ÷1 supply variation is dependent on coupling
from rising or falling trigger inputs and, to a lesser extent,
output polarity.
A very poor layout can actually degrade performance
further. The PCB layout should avoid routing SET next to
TRIG (or any other fast-edge, wide-swing signal).
APPLICATIONS INFORMATION
Figure 10. Typical Settling Time
VCTRL
2V/DIV
TRIG
5V/DIV
OUT
5V/DIV
PULSE WIDTH
2s/DIV
LTC6993-1
V+ = 3.3V
DIVCODE = 0
RSET = 200k
RMOD = 464k
tOUT = 3s AND 6s
20s/DIV
69931234 F10
SUPPLY (V)
2
–1.0
DRIFT
(%)
–0.8
–0.4
–0.2
0
1.0
0.4
3
4
69931234 F11
–0.6
0.6
0.8
0.2
5
6
RSET = 50k
NDIV = 1
LTC6993-1
POL = 0
LTC6993-1
POL = 1
LTC6993-3
POL = 1
LTC6993-3
POL = 0
Figure 11. tOUT Drift vs Supply Voltage
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