substitute 619k if a –0." />
參數(shù)資料
型號(hào): LTC6993HDCB-1#TRMPBF
廠商: Linear Technology
文件頁(yè)數(shù): 9/26頁(yè)
文件大?。?/td> 0K
描述: IC MONOSTABLE MULTIVIBRATOR 6DFN
產(chǎn)品培訓(xùn)模塊: TimerBlox Family Timing Devices
特色產(chǎn)品: TimerBlox?
標(biāo)準(zhǔn)包裝: 500
系列: LTC®6993
邏輯類型: 單穩(wěn)態(tài)
獨(dú)立電路: 1
施密特觸發(fā)器輸入: 無(wú)
傳輸延遲: 11ns
輸出電流高,低: 16mA,16mA
電源電壓: 2.25 V ~ 5.5 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 6-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 6-DFN-EP(2x3)
包裝: 帶卷 (TR)
配用: DC1562A-D-ND - BOARD EVAL LTC6992-2
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
17
69931234fb
Since 625k is not available as a standard 1% resistor,
substitute 619k if a –0.97% shift in tOUT is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 7.
APPLICATIONS INFORMATION
Figure 7. 100s Negative Pulse Generator
LTC6993-2
TRIG
GND
SET
OUT
V+
DIV
R1
102k
DIVCODE = 14
69931234 F07
2.25V TO 5.5V
R2
976k
0.1F
RSET
625k
Figure 8. Voltage-Controlled Pulse Width
LTC6993
TRIG
GND
SET
OUT
V+
DIV
R1
C1
0.1F
69931234 F08
V+
R2
RSET
RMOD
VCTRL
69931234 F09
LTC6993
TRIG
GND
SET
OUT
V+
DIV
C1
0.1F
R1
R2
V+
RMOD
RSET
+
V+
0.1F
1/2
LTC6078
LTC1659
V+
VCC
REF
GND
VOUT
P
DIN
CLK
CS/LD
NDIV RMOD
50k
tOUT =
DIN = 0 TO 4095
1+
RMOD
RSET
DIN
4096
1s
0.1F
Voltage-Controlled Pulse Width
With one additional resistor, the LTC6993 output pulse
widthcanbemanipulatedbyanexternalvoltage.Asshown
in Figure 8, voltage VCTRL sources/sinks a current through
RMOD to vary the ISET current, which in turn modulates
the pulse width as described in Equation (3).
tOUT =
NDIV RMOD
50k
1s
1
+
RMOD
RSET
VCTRL
VSET
(3)
Digital Pulse Width Control
The control voltage can be generated by a DAC (digital-to-
analog converter), resulting in a digitally-controlled pulse
width. Many DACs allow for the use of an external refer-
ence. If such a DAC is used to provide the VCTRL voltage,
the VSET dependency can be eliminated by buffering VSET
and using it as the DAC’s reference voltage, as shown in
Figure 9. The DAC’s output voltage now tracks any VSET
variation and eliminates it as an error source. The SET pin
cannot be tied directly to the reference input of the DAC
because the current drawn by the DAC’s REF input would
affect the pulse width.
Figure 9. Digitally Controlled Pulse Width
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