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參數(shù)資料
| 型號(hào)： | LTC6994CDCB-1#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/26頁 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 6-DFN |
| 產(chǎn)品培訓(xùn)模塊： | TimerBlox Family Timing Devices |
| 產(chǎn)品目錄繪圖： | LTC699_DFN |
| 特色產(chǎn)品： | TimerBlox? |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TimerBlox® |
| 功能： | 可編程 |
| 可用的總延遲： | 1µs ~ 33.6s |
| 獨(dú)立延遲數(shù)： | 1 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 配用： | DC1562A-E-ND - BOARD EVAL LTC6992-3 |
| 其它名稱： | LTC6994CDCB-1#TRMPBFDKR |
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LTC6994-1/LTC6994-2
16
699412fb
applicaTions inForMaTion
Basic Operation
The simplest and most accurate method to program the
LTC6994 is to use a single resistor, RSET, between the SET
and GND pins. The design procedure is a 3-step process.
Alternatively, Linear Technology offers the easy-to-use
TimerBlox Designer tool to quickly design any LTC6994
based circuit. Download the free TimerBlox Designer
software at www.linear.com/timerblox.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
Choose LTC6994-1 to delay one (rising or falling) input
transition. The POL bit then defines which edge is to be
delayed. POL = 0 delays rising edges. POL = 1 delays
falling edges.
Choose LTC6994-2 to delay rising and falling edges. Set
POL = 0 for normal operation, or POL = 1 to invert the
output.
Step 2: Select the NDIV Frequency Divider Value.
As explained earlier, the voltage on the DIV pin sets the
DIVCODE which determines both the POL bit and the
NDIV value. For a given delay time (tDELAY), NDIV should
be selected to be within the following range:
tDELAY
16s
≤NDIV ≤
tDELAY
1s
(1)
To minimize supply current, choose the lowest NDIV value.
However,insomecasesahighervalueforNDIVwillprovide
better accuracy (see Electrical Characteristics).
Table 1 can also be used to select the appropriate NDIV
values for the desired tDELAY.
With POL already chosen, this completes the selection of
DIVCODE. Use Table 1 to select the proper resistor divider
or VDIV/V+ ratio to apply to the DIV pin.
Step 3: Calculate and Select RSET.
The final step is to calculate the correct value for RSET
using the following equation:
RSET =
50k
1s
tDELAY
NDIV
(2)
Select the standard resistor value closest to the calculated
value.
Example: Design a circuit to delay falling edges by
tDELAY = 100s with minimum power consumption.
Step 1: Select the LTC6994 Version and POL Bit
Setting.
To delay negative transitions, choose the LTC6994-1 with
POL = 1.
Step 2: Select the NDIV Frequency Divider Value.
Choose an NDIV value that meets the requirements of
Equation (1), using tDELAY = 100s:
6.25 ≤ NDIV ≤ 100
Potential settings for NDIV include 8 and 64. NDIV = 8 is
the best choice, as it minimizes supply current by us-
ing a large RSET resistor. POL = 1 and NDIV = 8 requires
DIVCODE = 14. Using Table 1, choose R1 = 102k and R2
= 976k values to program DIVCODE = 14.
Step 3: Select RSET.
Calculate the correct value for RSET using Equation (2).
RSET =
50k
1s
100s
8
= 625k
Since 625k is not available as a standard 1% resistor,
substitute 619k if a –0.97% shift in tDELAY is acceptable.
Otherwise, select a parallel or series pair of resistors such
as 309k and 316k to attain a more precise resistance.
The completed design is shown in Figure 9.
Figure 9. 100s Negative-Edge Delay
LTC6994-1
IN
GND
SET
OUT
V+
DIV
R1
102k
0.1F
DIVCODE = 14
699412 F09
2.25V TO 5.5V
R2
976k
RSET
625k
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| LTC6994CDCB-2#TRMPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| LTC6994CDCB-2#TRPBF | 功能描述:IC DELAY LINE 6-DFN RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| LTC6994CDCB-2TRMPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:TimerBlox: Delay Block/ Debouncer |
| LTC6994CS6-1#PBF | 制造商:Linear Technology 功能描述:SC-Timing, Cut Tape Delay with Rising or Falling Edge Trigger |
| LTC6994CS6-1#TRMPBF | 功能描述:IC DELAY LINE TSOT-23-6 RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:TimerBlox® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
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