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參數(shù)資料
| 型號： | LTM9011CY-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/40頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT UMODULE 140BGA |
| 標(biāo)準(zhǔn)包裝： | 210 |
| 系列： | µModule® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | Serial LVDS |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 1.33W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 140-BFBGA |
| 供應(yīng)商設(shè)備封裝： | 140-BGA（11.25x9） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 8 Differential; 8 Single-Ended |
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LTM9011-14/
LTM9010-14/LTM9009-14
26
9009101114fa
applicaTions inForMaTion
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to3.3VCMOSlogiclevelscanbeused.TheENC+threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25s to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
DIGITAL OUTPUTS
The digital outputs of the LTM9011-14/LTM9010-14/
LTM9009-14 are serialized LVDS signals. Each channel
outputs two bits at a time (2-lane mode). At lower sam-
pling rates there is a one bit per channel option (1-lane
mode). The data can be serialized with 16, 14, or 12-bit
serialization (see the Timing Diagrams section for details).
Note that with 12-bit serialization the two LSBs are not
available—this mode is included for compatibility with
12-bit versions of these parts.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversion result begins. In the 2-lane, 14-bit serialization
mode, the frequency of the FR output is halved.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100 differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9011-14. The
Sampling Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTM9010-14) or 80MHz (LTM9009-14).
SERIALIZATION MODE
MAXIMUM SAMPLING
FREQUENCY, fS (MHz)
DCO FREQUENCY
FR FREQUENCY
SERIAL DATA RATE
2-Lane
16-Bit Serialization
125
4 fS
fS
8 fS
2-Lane
14-Bit Serialization
125
3.5 fS
0.5 fS
7 fS
2-Lane
12-Bit Serialization
125
3 fS
fS
6 fS
1-Lane
16-Bit Serialization
62.5
8 fS
fS
16 fS
1-Lane
14-Bit Serialization
71.4
7 fS
fS
14 fS
1-Lane
12-Bit Serialization
83.3
6 fS
fS
12 fS
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