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參數(shù)資料
| 型號(hào)： | LU6X14FT |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | LU6X14FT |
Product Brief
August 2000
LU6X14FT
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
Description
The LU6X14FT is a quad transceiver for serial data
transmission over fiber or coaxial media from
1.0 Gbits/s—3.125 Gbits/s. The device is available in
a 208-pin PBGAM package. The block diagram of the
chip is shown in Figure 1 on page 2. The transmitter
section accepts either 8-bit unencoded data or 10-bit
encoded data at the parallel input port. It also
accepts the low-speed system clock at the REFCLK
input and uses this clock to synthesize the internal
high-speed serial bit clock. In the 1.0 Gbits/s—
1.25 Gbits/s mode, the parallel input data is latched
on the falling edge of the low-speed TBC clock. In the
2.0 Gbits/s to 3.125 Gbits/s mode, the parallel input
data is framed by the rising and falling edges of the
low-speed TBC clock. REFCLK and TBC clock are
required to be the same frequency, but the phase
relationship is arbitrary. The serialized data is avail-
able at the differential CML output, terminated by
50
or 75
, to drive either an optical transmitter or
coaxial media.
The receive section receives high-speed serial data
at its differential CML input port. This data is fed to
the clock recovery section which generates a recov-
ered clock and retimes the data. The retimed data is
deserialized and presented as a 10-bit encoded or a
8-bit unencoded parallel data on the output port.
Two-phase receive byte clocks are available synchro-
nous with the parallel words. The receiver also recog-
nizes the comma characters and aligns the bit
stream to the proper word boundary.
The quad transceiver is controlled and configured
with an 8-bit microprocessor interface. Each channel
has dedicated registers that are readable and writ-
able. The quad device also contains global registers
for control of common circuitry and functions.
Potential Applications
I
Stand-alone transceiver product.
I
Transceiver macrocell template.
Features
I
Designed to operate in Ethernet, fibre channel,
FireWire*, or backplane applications.
I
Operationally compliant with the fibre channel
X3T11. Provides FC-0 services at 1.0 Gbits/s—
1.25 Gbits/s, 2.0 Gbits/s—2.5 Gbits/s, and
3.125 Gbits/s.
I
Selectable data rate (1.0 Gbits/s—1.25 Gbits/s,
2.0 Gbits/s—2.5 Gbits/s, and 3.125 Gbits/s).
I
100 MHz—156 MHz differential CML or single-
ended CMOS reference clock.
I
8-bit/10-bit parallel I/O interface.
I
Programmable control and configuration interface
to define the various device configurations.
I
Automatic lock to reference in absence of receive
data.
I
CML high-speed interface I/O for use with optical
transceiver, coaxial copper media, or shielded
twisted pairs.
I
Programmable transmit pre-emphasis optimized
for backplanes.
I
Requires one external resistor for bias current gen-
eration.
I
Requires no external components for clock recov-
ery and frequency synthesis.
I
Under 250 mW per transceiver.
I
Low powerdown dissipation.
I
1.5 V ± 5% power supply.
I
1.8 V ± 5% power supply option for differential high
speed I/O circuits.
I
–40 °C—70 °C ambient temperature.
* FireWire is a registered trademark of Apple Computer, Inc.
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