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| 型號(hào)： | LU6X14FT |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 161K |
| 代理商： | LU6X14FT |
Lucent Technologies Inc.
5
Product Brief
August 2000
1.0—1.25/2.0—2.5/3.125 Gbits/s SERDES
LU6X14FT
Block Diagrams
(continued)
0608 (F)
Figure 4. Clock Management
Functional Description
Bias Section
A fractional band-gap voltage generator is included on the chip. A precision external resistor connected between
the pins RESIN and RESRT is used to generate the bias currents within the chip. The value of this resistor should
be 3.32 k
± 1%. The current handling capability of this resistor should be at least 300
μ
A.
Transmit/Receive Data Rate Selection
The high-speed transmit and receive serial data can operate at 1.0 Gbits/s—1.25 Gbits/s or 2.0 Gbits/s—
3.125 Gbits/s, depending on the state of the TXHR and RXHR control bits from the microprocessor interface. The
REFCLK and TBC clock are always frequency synchronous. Table 1 shows the relationship between the data rates
and the input and recovered clocks.
Table 1. Input and Recovered Clock Rates for Different Data Rates
Data Rate
1.0 Gbits/s
1.25 Gbits/s
2.0 Gbits/s
2.5 Gbits/s
3.125 Gbits/s
TBC/Reference Clock
100 MHz
125 MHz
100 MHz
125 MHz
156 MHz
RBC[0:1]
50 MHz
62.5 MHz
100 MHz
125 MHz
156 MHz
PARALLEL
TRANSMIT
CLOCK
÷2
TBC
T
X
PLL
XCK
REFCLK
HIGH-SPEED
TRANSMIT
CLOCK
RBC[0—1]
CONTROLLER
TXHR
RXHR
RECEIVER
TBCKSEL
TXHR
LOOPENB
TBC ÷ 2
TBC
XCK
RBC[0—1]
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