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參數(shù)資料
| 型號： | LUCL8567AP-DT |
| 英文描述： | SLIC for Peoples Republic of China Applications |
| 中文描述： | 為人民共和國的中國用戶接口的應(yīng)用 |
| 文件頁數(shù)： | 16/42頁 |
| 文件大?。?/td> | 701K |
| 代理商： | LUCL8567AP-DT |
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16
Lucent Technologies Inc.
Data Sheet
August 1999
People’s Republic of China Applications
L8567 SLIC for
Electrical Characteristics
(continued)
Ring Trip Requirements
I
Ringing signal:
— Voltage, minimum 35 Vrms, maximum 100 Vrms.
— Frequency, 17 Hz to 28 Hz.
— Crest factor, 1.4 to 2.
I
Ringing trip:
—
≤
100 ms (typical),
≤
250 ms (V
BAT
= –33 V, loop
length = 530
).
I
Pretrip:
— The circuits in Figure 4 will not cause ringing trip.
5-5841 (F)
Figure 4. Ring Trip Circuits
RING
RING
RING
100
10 k
8 μF
TIP
TIP
TIP
2
μ
F
200
SWITCH CLOSES < 12 ms
Table 11. Timing Requirements (DI, EN, DO, and RD), CCLK = 2.048 MHz
1. Unless otherwise specified, all times are measured from the 50% point of logic transitions.
2. This parameter is not tested in production. It is guaranteed by design and device characterization.
5-5808a
Figure 5. Timing Requirements
Symbol
t
R
, t
F
Parameter
1
Min
0
Max
75
Unit
ns
Input Rise and Fall Time EN (10% to 90%)
2
Maximum Input Capacitance
2
Propagation Delay EN to DO
2
Propagation Delay EN to RD Outputs
2
Minimum Setup Time from DI to EN
2
Minimum Hold Time from EN to DI
2
Minimum Pulse Width of EN
2
C
IN
—
5
pF
t
PD01
0
977
ns
t
PDR
0
10
μ
s
t
SDC
488
—
ns
t
HED
488
—
ns
t
WEN
1465
—
μ
s
tWEN
CCLK
EN
NSTAT/NTSD
tSDC
RD1, RD2, RD3
CSEL
B0/B1
tPD01
tHED
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