參數(shù)資料
型號： LUCL9310GP-D
英文描述： Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device
中文描述： 線路接口和線路接入電路全功能用戶接口，振鈴繼電器，測試接入設備
文件頁數(shù)： 54/60頁
文件大小： 1053K
代理商： LUCL9310GP-D
Data Sheet
July 2001
Full-Feature SLIC, Ringing Relay, and Test Access Device
L9310 Line Interface and Line Access Circuit
54
Agere Systems Inc.
ac Applications
(continued)
First-Generation Codec ac Interface Network: Complex Termination
(continued)
Basic Loop Start Application Using T7504 Type Codec
12-3528b (F)
Notes:
Termination impedance = 220
+ (820
|| 115 nF).
Hybrid balance = 220
+ (820
|| 115 nF).
Tx = 0 dBm.
Rx = 0 dBm.
Figure 19
.
Basic Loop Start Application Using T7504 Type Codec
R
S2
FUSIBLE
OR PTC
50
C
VBAT1
0.1
F
V
BAT1
RCVN
RTS
OVH (OVERHEAD = 9.2 V for 2.2 Vrms PPM)
V
PROG
(I
LIMIT
= 25 mA)
V
BAT
LCF
C
F2
0.015
μ
F
FB2
FB1
CF1
VTX
RCVP
R
49.9 k
R
RCV
R
HB1
113 k
VFXIN
GSX
V
FRO
DX
DR
FSE
FSEP
MCLK
ASEL
1/4 T7504
CODEC
CONTROL
INPUTS
PCM
HIGHWAY
SYNC
AND
CLOCK
–
+
NSTAT
ITR
PPMOUT
C
RTS
0.1
μ
F
PPMIN
AGND V
DD
2.4 V
R
N2
47.5 k
V
REF
1 M
50
R
RING
T
RING
100 V—130 V
SECONDARY
PROTECTOR
FUSIBLE
OR PTC
R
RTF
400
RINGING
SOURCE
C
CC
0.1
μ
F
V
CC
C
DD
0.1
μ
F
V
DD
A
D
C
TX
0.15
μ
F
R
GX
6.34 k
C
0.33
μ
F
RSW
PT
PWR
V
/
V
CC
BGND
V
BAT1
TRGDET
ICM
DGND
TXI
TXN
VITR
180 V—330 V
SECONDARY
PROTECTOR
V
REF
B3
RESET
LATCH
B2 B1 B0
V
REF
TESTLEV TESTSIG
CF2
MULTIPLEXED
DATA BUS
TO/FROM
MICROPROCESSOR
PER-LINE
TO/FROM
MICROPROCESSOR
V
BAT2
C
VBAT2
0.1
μ
F
C
PPM
0.1
μ
F
C
GS
12 nF
R
TGS
1.74 k
R
PPM
17.4 k
R
X
R
T6
40.2 k
R
127 k
R
54.9 k
RAMPED
PPM
GENERATION
0.7 Vrms for
2.2 Vrms at T/R
59.0 k
C
C2
0.1
μ
F
N
1C
115 k
59 k
L9310
(GAIN OF 8)
R
69.8 k
R
PR
R
VPROG
23.2 k
16.9 k
R
OVH
LCTH (10 mA)
V
REF
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