參數(shù)資料
型號: LUCW3000CCN
英文描述: W3000 PLL Dual-Band Frequency Synthesizer
中文描述: W3000鎖相環(huán)雙頻段頻率合成器
文件頁數(shù): 15/28頁
文件大小: 327K
代理商: LUCW3000CCN
Advance Data Sheet
December 1999
W3000 PLL Dual-Band Frequency Synthesizer
Lucent Technologies Inc.
15
MAIN Register
The MAIN register is intended for programming that can occur frequently for dynamic channel switching and
putting the W3000 into power-saving mode.
Table 18. MAIN Register Bit Description (C0 = 0, C1 = 0)
Bit
1
2:8
9:19
20
21
22
23
24
Name
C0 = 0
A[1:7]
M[1:11]
Reserved
Reserved
EN2
B
C1 = 0
Description
Register address bit. C0 = 0 for MAIN (last bit in serial sequence).
Swallow counter for prescaler modulus control.
Main counter.
Enable all PLL circuits (0 = powerdown mode).
Band select for charge pump current control (band 1 = 0, band 2 = 1).
Secondary address bit.
Table 19. MAIN Register
Last bit in serial sequence
1
2
A
1
3
A
2
4
A
3
5
A
4
6
A
5
7
A
6
8
A
7
9
M
1
10
M
2
11
M
3
12
M
4
13
M
5
14
M
6
15
M
7
16
M
8
17
M
9
18
M
10
19
M
11
20
X
21
X
22
EN
23
B
24
C1
= 0
C0
= 0
Note: X bits are don’t care bits.
Table 20. A1:A7: Swallow Counter Count (Bits 2 to 8)
A7
Bit 8
0
0
0
.
.
.
0
.
.
.
1
A6
Bit 7
0
0
0
.
.
.
1
.
.
.
1
A5
Bit 6
0
0
0
.
.
.
1
.
.
.
1
A4
Bit 5
0
0
0
.
.
.
1
.
.
.
1
A3
Bit 4
0
0
0
.
.
.
1
.
.
.
1
A2
Bit 3
0
0
1
.
.
.
1
.
.
.
1
A1
Bit 2
0
1
0
.
.
.
1
.
.
.
1
Counter Ratio
0
1
2
.
.
.
63
.
.
.
127
First bit in serial sequence
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